Inventor
Huicheng Chang
Inventor
Tainan, TW
Overview
Patents· 60 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices31%
H01LSemiconductor devices30%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
B82YSpecific uses or applications of nanostructures1%
H10BElectronic memory devices1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,879,371Thermal treatment for gate dielectrics202010,867,859Methods of fabricating semiconductor devices having isolation structures with liners202010,867,869Method for patterning a lanthanum containing layer202010,868,178Field effect transistor contact with reduced contact resistance using implantation process202010,868,142Gate spacer structure and method of forming same202010,861,957FinFET devices and methods of forming202010,854,471Process for making multi-gate transistors and resulting structures202010,770,570FinFET device and methods of forming202010,763,168Semiconductor structure with doped via plug and method for forming the same202010,763,363Gradient doped region of recessed fin forming a FinFET device202010,727,226Semiconductor structure and method for forming the same202010,714,348Semiconductor device having hydrogen in a dielectric layer202010,714,344Mask formation by selectively removing portions of a layer that have not been implanted202010,658,510Source/drain structure202010,643,892Metal loss prevention using implantation202010,566,242Minimization of plasma doping induced fin height loss202010,553,718Semiconductor devices with core-shell structures202010,529,861FinFET structures and methods of forming the same202010,515,963Field effect transistor contact with reduced contact resistance201910,515,966Enhanced channel strain to reduce contact resistance in NMOS FET devices201910,510,854Semiconductor device having gate body and inhibitor film between conductive prelayer over gate body and conductive layer over inhibitor film201910,510,619Semiconductor structure and method for manufacturing the same201910,510,664Contact structure and formation thereof201910,510,891Field effect transistor contact with reduced contact resistance using implantation process201910,504,795Method for patterning a lanthanum containing layer201910,504,735Method of forming a semiconductor device by high-pressure anneal and post-anneal treatment201910,460,940Mask formation by selectively removing portions of a layer that have not been implanted201910,361,094Process for making multi-gate transistors and resulting structures201910,347,762Field effect transistor contact with reduced contact resistance using implantation process201910,347,720Doping for semiconductor device with conductive feature201910,326,003FinFET device and methods of forming201910,269,799Field effect transistor contact with reduced contact resistance201910,177,006Process for making multi-gate transistors and resulting structures201910,164,066FinFET devices and methods of forming201810,157,995Integrating junction formation of transistors with contact formation201810,115,808finFET device and methods of forming201810,056,383Enhanced channel strain to reduce contact resistance in NMOS FET devices201810,014,382Semiconductor device with sidewall passivation and method of making20189,812,451'Field effect transistor contact with reduced contact resistance'20179,735,107'Contact structure and formation thereof'20179,660,031'Integrated circuit device having III-V compound semiconductor region comprising magnesium and N-type impurity and overlying III-V compound semiconductor layer formed without Cp2Mg precursor'20179,607,838'Enhanced channel strain to reduce contact resistance in NMOS FET devices'20179,537,010'Semiconductor device structure and method for forming the same'20179,508,716'Methods of manufacturing a semiconductor device'20169,412,836'Contacts for transistors'20169,397,169'Epitaxial structures'20169,356,102'Double stepped semiconductor substrate'20169,287,170'Contact structure and formation thereof'20169,224,815'Method of tuning doping concentration in III-V compound semiconductor through co-doping donor and acceptor impurities'20159,123,564'Semiconductor device with conformal doping and method of making'20159,099,311'Double stepped semiconductor substrate'20159,064,959'Method and apparatus for forming a CMOS device'20159,048,087'Methods for wet clean of oxide layers over epitaxial layers'20159,029,246'Methods of forming epitaxial structures'20158,927,362'CMOS device and method of forming the same'20158,822,290'FinFETs and methods for forming the same'20148,680,576'CMOS device and method of forming the same'20148,497,177'Method of making a FinFET device'20138,394,694'Reliability of high-K gate dielectric layers'20137,842,983'Boundaries with elevated deuterium levels'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2013Patents assigned to INTEL CORP (2)· patent assignee history
2010Based in Portland, OR, US· patent location history
2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (13)· patent assignee history
2013–2014Patents assigned to CHANG HUICHENG (2)· patent assignee history
2013Patents assigned to ASHUTOSH ASHUTOSH (1)· patent assignee history
2013–2020Based in Tainan, TW· patent location history
2013Based in Beaverton, OR, US· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (45)· patent assignee history
2017Based in Hsinchu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 45 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 13 | 2013–2016 |
| CHANG HUICHENGself | 2 | 2013–2014 |
| INTEL CORP | 2 | 2010–2013 |
| ASHUTOSH ASHUTOSH | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tainan, TW | 57 | 2013–2020 |
| Hsinchu, TW | 1 | 2017 |
| Beaverton, OR, US | 1 | 2013 |
| Portland, OR, US | 1 | 2010 |