Inventor
Ulrike Gruening
Inventor
Wappingers Falls, NY, US
Overview
Patents· 57 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices47%
H10DInorganic electric semiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G11CStatic stores7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
PatentTitleYear
6,967,133'Method for fabricating a semiconductor structure'20056,812,091'Trench capacitor memory cell'20046,762,447'Field-shield-trench isolation for gigabit DRAMs'20046,759,291'Self-aligned near surface strap for high density trench DRAMS'20046,740,555'Semiconductor structures and manufacturing methods'20046,727,539'Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect'20046,630,379'Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch'20036,605,860'Semiconductor structures and manufacturing methods'20036,593,612'Structure and method for forming a body contact for vertical transistor cells'20036,593,613'Memory cell for plateline sensing'20036,573,137'Single sided buried strap'20036,555,862'Self-aligned buried strap for vertical transistors'20036,544,850'Dynamic random access memory'20036,486,024'Integrated circuit trench device with a dielectric collar stack, and method of forming thereof'20026,451,648'Process for buried-strap self-aligned to deep storage trench'20026,437,381'Semiconductor memory device with reduced orientation-dependent oxidation in trench structures'20026,437,388'Compact trench capacitor memory cell with body contact'20026,429,068'Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect'20026,429,092'Collar formation by selective oxide deposition'20026,426,251'Process for manufacturing a crystal axis-aligned vertical side wall device'20026,399,434'Doped structures containing diffusion barriers'20026,399,978'Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region'20026,376,324'Collar process for reduced deep trench edge bias'20026,372,567'Control of oxide thickness in vertical transistor structures'20026,369,419'Self-aligned near surface strap for high density trench DRAMS'20026,362,040'Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates'20026,359,299'Apparatus and method for forming controlled deep trench top isolation layers'20026,348,388'Process for fabricating a uniform gate oxide of a vertical transistor'20026,348,374'Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure'20026,339,241'Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch'20026,331,459'Use of dummy poly spacers and divot fill techniques for DT-aligned processing after STI formation for advanced deep trench capacitor DRAM'20016,327,170'Reducing impact of coupling noise in multi-level bitline architecture'20016,323,103'Method for fabricating transistors'20016,320,215'Crystal-axis-aligned vertical side wall device'20016,319,788'Semiconductor structure and manufacturing methods'20016,320,780'Reduced impact from coupling noise in diagonal bitline architectures'20016,291,335'Locally folded split level bitline wiring'20016,271,142'Process for manufacture of trench DRAM capacitor buried plates'20016,265,742'Memory cell structure and fabrication'20016,258,659'Embedded vertical DRAM cells and dual workfunction logic gates'20016,255,683'Dynamic random access memory'20016,255,158'Process of manufacturing a vertical dynamic random access memory device'20016,229,173'Hybrid 5F2 cell layout for buried surface strap aligned to vertical transistor'20016,204,140'Dynamic random access memory'20016,201,730'Sensing of memory cell via a plateline'20016,194,736'Quantum conductive recrystallization barrier layers'20016,194,755'Low-resistance salicide fill for trench capacitors'20016,190,971'Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region'20016,188,598'Reducing impact of coupling noise'20016,184,107'Capacitor trench-top dielectric for self-aligned device isolation'20016,184,091'Formation of controlled trench top isolation layers for vertical transistors'20016,177,698'Formation of controlled trench top isolation layers for vertical transistors'20016,153,902'Vertical DRAM cell with wordline self-aligned to storage trench'20006,150,670'Process for fabricating a uniform gate oxide of a vertical transistor'20006,093,614'Memory cell structure and fabrication'20006,074,909'Apparatus and method for forming controlled deep trench top isolation layers'20006,013,937'Buffer layer for improving control of layer thickness'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2004Patents assigned to IBM (36)· patent assignee history
2000–2004Patents assigned to INFINEON TECHNOLOGIES CORP (17)· patent assignee history
2000–2001Patents assigned to SIEMENS AG (6)· patent assignee history
2000–2004Based in Wappingers Falls, NY, US· patent location history
2001–2005Patents assigned to INFINEON TECHNOLOGIES AG (20)· patent assignee history
2001Patents assigned to SIEMENS MICROELECTRONICS (1)· patent assignee history
2001–2004Based in Munich, DE· patent location history
2005Based in München, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 36 | 2000–2004 |
| INFINEON TECHNOLOGIES AG | 20 | 2001–2005 |
| INFINEON TECHNOLOGIES CORP | 17 | 2000–2004 |
| SIEMENS AG | 6 | 2000–2001 |
| SIEMENS MICROELECTRONICS | 1 | 2001 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 34 | 2000–2004 |
| Munich, DE | 22 | 2001–2004 |
| München, DE | 1 | 2005 |