Inventor
Chia-Cheng Chou
Inventor
Keelung, TW
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1040%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H01LSemiconductor devices26%
H10DInorganic electric semiconductor devices6%
A63BApparatus for physical training, gymnastics, swimming, climbing, or fencing1%
PatentTitleYear
10,840,134Interconnect structure and method202010,707,165Semiconductor device having an extra low-k dielectric layer and method of forming the same202010,510,585Multi-patterning to form vias with straight profiles201910,312,107Forming interconnect structure using plasma treated metal hard mask201910,269,627Interconnect structure and method201910,163,691Low-K dielectric interconnect systems20189,981,153Brake controller for spinner bike20189,768,061'Low-k dielectric interconnect systems'20179,754,822'Interconnect structure and method'20179,748,134'Method of making interconnect structure'20179,679,804'Multi-patterning to form vias with straight profiles'20179,589,856'Automatically adjusting baking process for low-k dielectric material'20179,373,581'Interconnect structure and method for forming the same'20169,257,331'Method of making interconnect structure'20169,236,294'Method for forming semiconductor device structure'20169,196,551'Automatically adjusting baking process for low-k dielectric material'20159,087,877'Low-k interconnect structures with reduced RC delay'20159,004,914'Method of and apparatus for active energy assist baking'20158,993,442'Interconnect structure and method for forming the same'20158,877,083'Surface treatment in the formation of interconnect structure'20148,853,831'Interconnect structure and method for forming the same'20148,846,528'Method of modifying a low k dielectric layer having etched features and the resulting product'20148,629,056'Method for forming self-assembled mono-layer liner for cu/porous low-k interconnections'20148,481,412'Method of and apparatus for active energy assist baking'20138,354,346'Method for fabricating low-k dielectric and Cu interconnect'20138,043,959'Method of forming a low-k dielectric layer with improved damage resistance and chemical integrity'20117,998,873'Method for fabricating low-k dielectric and Cu interconnect'20117,968,451'Method for forming self-assembled mono-layer liner for Cu/porous low-k interconnections'20117,723,226'Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio'20107,485,949'Semiconductor device'20097,466,027'Interconnect structures with surfaces roughness improving liner and methods for fabricating the same'20087,314,828'Repairing method for low-k dielectric materials'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (19)· patent assignee history
2008–2020Based in Keelung, TW· patent location history
2013–2015Patents assigned to LIN KENG-CHU (6)· patent assignee history
2013–2015Patents assigned to CHOU CHIA-CHENG (5)· patent assignee history
2013–2015Patents assigned to KO CHUNG-CHI (5)· patent assignee history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (12)· patent assignee history
2017Based in Hsinchu, TW· patent location history
2018Based in Hsinchu County, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 19 | 2008–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 12 | 2016–2020 |
| LIN KENG-CHU | 6 | 2013–2015 |
| CHOU CHIA-CHENGself | 5 | 2013–2015 |
| KO CHUNG-CHI | 5 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Keelung, TW | 30 | 2008–2020 |
| Hsinchu County, TW | 1 | 2018 |
| Hsinchu, TW | 1 | 2017 |