Inventor
Tatsumi Shirasu
Inventor
Kawasaki, JP
Overview
Patents· 5 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices50%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1050%
PatentTitleYear
6,806,130'Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device'20046,630,375'Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device'20036,368,905'Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device'20026,043,114'Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device'20004,258,465'Method for fabrication of offset gate MIS device'1981Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1981–2003Patents assigned to HITACHI LTD (4)· patent assignee history
1981Based in Tokyo, JP· patent location history
2000–2004Based in Kawasaki, JP· patent location history
2004Patents assigned to RENESAS TECH CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HITACHI LTD | 4 | 1981–2003 |
| RENESAS TECH CORP | 1 | 2004 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kawasaki, JP | 4 | 2000–2004 |
| Tokyo, JP | 1 | 1981 |