Inventor
James Allan Kahle
Inventor
Austin, TX, US
Overview
Patents· 114 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing79%
H04LTransmission of digital information, e.g. telegraphic communication8%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
A47GHousehold or table equipment1%
B65DContainers for storage or transport of articles or materials, e.g. bags, barrels, bottles, boxes, cans, cartons, crates, drums, jars, tanks, hoppers, forwarding containers1%
G09GArrangements or circuits for control of indicating devices using static means to present variable information1%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
H04NPictorial communication, e.g. television1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
PatentTitleYear
11,016,908Distributed directory of named data elements in coordination namespace202110,831,663Tracking transactions using extended memory features202010,296,339Thread transition management201910,152,450Remote processing and memory utilization201810,120,810Implementing selective cache injection201810,055,226Thread transition management201810,049,061Active memory device gather, scatter, and filter20189,910,783'Implementing selective cache injection'20189,703,561'Thread transition management'20179,703,516'Configurable interface controller'20179,582,427'Implementing selective cache injection'20179,218,291'Implementing selective cache injection'20159,197,920'Shared media experience distribution and playback'20159,064,030'Tree traversal in a memory device'20159,037,669'Remote processing and memory utilization'20159,003,160'Active buffered memory'20158,725,993'Thread transition management'20148,516,272'Secure dynamically reconfigurable logic'20138,108,564'System and method for a configurable interface controller'20128,051,315'Power throttling apparatus'20118,032,849'Integrated circuit chip with modular design'20118,010,716'Methods and apparatus for supporting multiple configurations in a multi-processor system'20117,814,281'Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment'20107,802,023'Methods and apparatus for supporting multiple configurations in a multi-processor system'20107,720,982'Computer architecture and software cells for broadband networks'20107,721,123'Method and apparatus for managing the power consumption of a data processing system'20107,698,473'Methods and apparatus for list transfers using DMA transfers in a multi-processor system'20107,689,783'System and method for sharing memory by heterogeneous processors'20107,657,667'Method to provide cache management commands for a DMA controller'20107,650,491'Method and system for controlled distribution of application code and content data within a computer network'20107,647,433'System and method for flexible multiple protocols'20107,603,703'Method and system for controlled distribution of application code and content data within a computer network'20097,509,457'Non-homogeneous multi-processor system with shared memory'20097,496,673'SIMD-RISC microprocessor architecture'20097,496,776'Power throttling method and apparatus'20097,398,482'Modular design method and apparatus'20087,389,363'System and method for flexible multiple protocols'20087,356,713'Method and apparatus for managing the power consumption of a data processing system'20087,321,958'System and method for sharing memory by heterogeneous processors'20087,299,372'Hierarchical management for multiprocessor system with real-time attributes'20077,299,371'Hierarchical management for multiprocessor system'20077,233,998'Computer architecture and software cells for broadband networks'20077,200,689'Cacheable DMA'20077,120,748'Software-controlled cache set management'20067,114,042'Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment'20067,114,035'Software-controlled cache set management with software-generated class identifiers'20067,107,363'Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation'20067,103,748'Memory management for real-time applications'20067,093,080'Method and apparatus for coherent memory structure of heterogeneous processor systems'20067,062,612'Updating remote locked cache'20067,010,626'DMA prefetch'20066,981,072'Memory management in multiprocessor system'20056,970,982'Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions'20056,961,820'System and method for identifying and accessing streaming data in a locked portion of a cache'20056,931,493'Implementation of an LRU and MRU algorithm in a partitioned cache'20056,907,477'Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors'20056,848,044'Circuits and methods for recovering link stack data upon branch instruction mis-speculation'20056,820,143'On-chip data transfer in multi-processor system'20046,785,841'Processor with redundant logic'20046,779,049'Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism'20046,766,442'Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value'20046,728,866'Partitioned issue queue and allocation strategy'20046,725,354'Shared execution unit in a dual core processor'20046,697,939'Basic block cache microprocessor with instruction history information'20046,678,820'Processor and method for separately predicting conditional branches dependent on lock acquisition'20046,662,294'Converting short branches to predicated instructions'20036,662,360'Method and system for software control of hardware branch prediction mechanism in a data processor'20036,658,555'Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline'20036,658,558'Branch prediction circuit selector with instruction context related condition type determining'20036,654,869'Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling'20036,631,463'Method and apparatus for patching problematic instructions in a microprocessor using software interrupts'20036,629,233'Secondary reorder buffer microprocessor'20036,609,190'Microprocessor with primary and secondary issue queue'20036,574,712'Software prefetch system and method for predetermining amount of streamed data'20036,543,003'Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor'20036,543,002'Recovery from hang condition in a microprocessor'20036,539,500'System and method for tracing'20036,477,635'Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing'20026,473,850'System and method for handling instructions occurring after an ISYNC instruction'20026,460,115'System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism'20026,430,678'Scoreboard mechanism for serialized string operations utilizing the XER'20026,298,436'Method and system for performing atomic memory accesses in a processor system'20016,212,542'Method and system for executing a program within a multiscalar processor by processing linked thread descriptors'20016,209,081'Method and system for nonsequential instruction dispatch and execution in a superscalar processor system'20015,995,743'Method and system for interrupt handling during emulation in a data processing system'19995,978,896'Method and system for increased instruction dispatch efficiency in a superscalar processor system'19995,956,495'Method and system for processing branch instructions during emulation in a data processing system'19995,930,484'Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access'19995,926,628'Selectable priority bus arbitration scheme'19995,913,925'Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order'19995,913,044'Method and system for simultaneous variable-width bus access in a multiprocessor system'19995,901,294'Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access'19995,898,864'Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors'19995,898,882'Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage'19995,870,575'Indirect unconditional branches in data processing system emulation mode'19995,867,684'Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction'19995,812,823'Method and system for performing an emulation context save and restore that is transparent to the operating system'19985,802,386'Latency-based scheduling of instructions in a superscalar processor'19985,764,942'Method and system for selective serialization of instruction processing in a superscalar processor system'19985,764,969'Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization'19985,761,473'Method and system for increased instruction synchronization efficiency in a superscalar processsor system utilizing partial data dependency interlocking'19985,758,141'Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register'19985,758,120'Method and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bits'19985,758,140'Method and system for emulating instructions by performing an operation directly using special-purpose register contents'19985,748,938'System and method for maintaining coherency of information transferred between multiple devices'19985,732,235'Method and system for minimizing the number of cycles required to execute semantic routines'19985,732,005'Single-precision, floating-point register array for floating-point units performing double-precision operations by emulation'19985,715,420'Method and system for efficient memory management in a data processing system utilizing a dual mode translation lookaside buffer'19985,694,565'Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions'19975,539,681'Circuitry and method for reducing power consumption within an electronic circuit'19965,467,473'Out of order instruction load and store comparison'19955,465,373'Method and system for single cycle dispatch of multiple instructions in a superscalar processor system'19955,420,808'Circuitry and method for reducing power consumption within an electronic circuit'19955,075,840'Tightly coupled multiprocessor instruction synchronization'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2021Patents assigned to IBM (112)· patent assignee history
1991–2021Based in Austin, TX, US· patent location history
2010–2011Patents assigned to SONY COMPUTER ENTERTAINMENT INC (4)· patent assignee history
2013–2018Patents assigned to KAHLE JAMES A (6)· patent assignee history
2015–2018Patents assigned to CHEN DONG (2)· patent assignee history
2015–2018Patents assigned to EISLEY NOEL A (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 112 | 1991–2021 |
| KAHLE JAMES Aself | 6 | 2013–2018 |
| SONY COMPUTER ENTERTAINMENT INC | 4 | 2010–2011 |
| CHEN DONG | 2 | 2015–2018 |
| EISLEY NOEL A | 2 | 2015–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 114 | 1991–2021 |