Inventor
Anthony D. Polson
Inventor
Jericho, VT, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing47%
G01RMeasuring electric variables29%
H03KPulse technique12%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
G11CStatic stores3%
H10DInorganic electric semiconductor devices3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
PatentTitleYear
9,310,426'On-going reliability monitoring of integrated circuit chips in the field'20169,075,106'Detecting chip alterations with light emission'20158,336,008'Characterization of long range variability'20127,962,874'Method and system for evaluating timing in an integrated circuit'20117,890,906'Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells'20117,877,714'System and method to optimize semiconductor power by integration of physical design timing and product performance measurements'20117,870,525'Slack sensitivity to parameter variation based timing analysis'20117,865,861'Method of generating wiring routes with matching delay in the presence of process variation'20117,849,433'Integrated circuit with uniform polysilicon perimeter density, method and design structure'20107,840,863'Functional frequency testing of integrated circuits'20107,840,864'Functional frequency testing of integrated circuits'20107,823,115'Method of generating wiring routes with matching delay in the presence of process variation'20107,810,054'Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point'20107,805,693'IC chip design modeling using perimeter density to electrical characteristic correlation'20107,765,351'High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips'20107,716,616'Slack sensitivity to parameter variation based timing analysis'20107,680,626'System and method of analyzing timing effects of spatial distribution in circuits'20107,521,973'Clock-skew tuning apparatus and method'20097,489,204'Method and structure for chip-level testing of wire delay independent of silicon delay'20097,487,487'Design structure for monitoring cross chip delay variation on a semiconductor device'20097,444,608'Method and system for evaluating timing in an integrated circuit'20087,418,689'Method of generating wiring routes with matching delay in the presence of process variation'20087,401,307'Slack sensitivity to parameter variation based timing analysis'20087,302,673'Method and system for performing shapes correction of a multi-cell reticle photomask design'20077,290,191'Functional frequency testing of integrated circuits'20077,280,939'System and method of analyzing timing effects of spatial distribution in circuits'20077,089,143'Method and system for evaluating timing in an integrated circuit'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2016Patents assigned to IBM (27)· patent assignee history
2006–2016Based in Jericho, VT, US· patent location history
2012–2015Patents assigned to POLSON ANTHONY D (2)· patent assignee history
2012Patents assigned to CULP JAMES A (1)· patent assignee history
2015Patents assigned to BERNSTEIN KERRY (1)· patent assignee history
2015Patents assigned to CULP JAMES (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 27 | 2006–2016 |
| POLSON ANTHONY Dself | 2 | 2012–2015 |
| BERNSTEIN KERRY | 1 | 2015 |
| CULP JAMES | 1 | 2015 |
| CULP JAMES A | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Jericho, VT, US | 27 | 2006–2016 |