Inventor
Rafael Rios
Inventor
Portland, OR, US
Overview
Patents· 66 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
H01LSemiconductor devices25%
B82YSpecific uses or applications of nanostructures14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G11CStatic stores3%
H10BElectronic memory devices3%
H03KPulse technique2%
B81BMicrostructural devices or systems, e.g. micromechanical devices1%
G06FElectric digital data processing1%
PatentTitleYear
11,031,503Non-planar gate thin film transistor202110,991,799Silicon and silicon germanium nanowire structures202110,964,701Vertical shared gate thin-film transistor-based charge storage memory202110,950,301Two transistor, one resistor non-volatile gain cell memory and storage element202110,930,791Systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in source and drain for low access and contact resistance of thin film transistors202110,878,889High retention time memory element with dual gate devices202010,847,653Semiconductor device having metallic source and drain regions202010,847,656Fabrication of non-planar IGZO devices for improved electrostatics202010,825,752Integrated thermoelectric cooling202010,804,357Integration methods to fabricate internal spacers for nanowire devices202010,734,511High mobility asymmetric field effect transistors with a band-offset semiconductor drain spacer202010,727,138Integration of single crystalline transistors in back end of line (BEOL)202010,659,046Local cell-level power gating switch202010,644,140Integrated circuit die having back-end-of-line transistors202010,644,123Systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors202010,644,111Strained silicon layer with relaxed underlayer202010,636,871Silicon and silicon germanium nanowire structures202010,593,804Non-planar semiconductor device having hybrid geometry-based active region202010,586,868Non-planar semiconductor device having hybrid geometry-based active region202010,580,860Integration methods to fabricate internal spacers for nanowire devices202010,580,899Nanowire structures having non-discrete source and drain regions202010,535,770Scaled TFET transistor formed using nanowire with surface termination202010,423,203Flip-flop circuit with low-leakage transistors201910,424,580Semiconductor devices having modulated nanowire counts201910,403,733Dielectric metal oxide cap for channel containing germanium201910,340,275Stackable thin film memory201910,283,589Integration methods to fabricate internal spacers for nanowire devices201910,249,742Offstate parasitic leakage reduction for tunneling field effect transistors201910,121,856Integration methods to fabricate internal spacers for nanowire devices201810,115,822Methods of forming low band gap source and drain structures in microelectronic devices201810,074,573CMOS nanowire structure201810,026,829Semiconductor device with isolated body portion20189,978,636Isolated and bulk semiconductor devices formed on a same bulk substrate20189,947,805Nanowire-based mechanical switching device20189,911,835'Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs'20189,859,368'Integration methods to fabricate internal spacers for nanowire devices'20189,842,643'Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors'20179,825,130'Leakage reduction structures for nanowire transistors'20179,608,059'Semiconductor device with isolated body portion'20179,595,581'Silicon and silicon germanium nanowire structures'20179,583,487'Semiconductor device having metallic source and drain regions'20179,583,491'CMOS nanowire structure'20179,583,602'Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs'20179,564,522'Nanowire structures having non-discrete source and drain regions'20179,490,780'Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors'20169,484,447'Integration methods to fabricate internal spacers for nanowire devices'20169,425,212'Isolated and bulk semiconductor devices formed on a same bulk substrate'20169,412,872'N-type and P-type tunneling field effect transistors (TFETs)'20169,362,074'Nanowire-based mechanical switching device'20169,224,810'CMOS nanowire structure'20159,129,829'Silicon and silicon germanium nanowire structures'20159,087,863'Nanowire structures having non-discrete source and drain regions'20159,029,221'Semiconductor devices having three-dimensional bodies with modulated heights'20158,890,120'Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs'20148,853,741'Junctionless accumulation-mode devices on decoupled prominent architectures'20148,753,942'Silicon and silicon germanium nanowire structures'20148,507,948'Junctionless accumulation-mode devices on prominent architectures, and methods of making same'20138,273,626'Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication'20127,973,389'Isolated tri-gate transistor fabricated on bulk substrate'20117,820,513'Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication'20107,456,476'Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication'20087,091,560'Method and structure to decrease area capacitance within a buried insulator device'20066,960,517'N-gate transistor'20056,867,104'Method to form a structure to decrease area capacitance within a buried insulator device'20056,489,655'Integrated circuit with dynamic threshold voltage'20026,261,878'Integrated circuit with dynamic threshold voltage'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2021Patents assigned to INTEL CORP (65)· patent assignee history
2001–2021Based in Portland, OR, US· patent location history
2012–2019Patents assigned to RIOS RAFAEL (17)· patent assignee history
2013–2019Patents assigned to KUHN KELIN J (14)· patent assignee history
2013–2019Patents assigned to CAPPELLANI ANNALISA (12)· patent assignee history
2014–2019Patents assigned to KIM SEIYON (10)· patent assignee history
2017–2021Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 65 | 2001–2021 |
| RIOS RAFAELself | 17 | 2012–2019 |
| KUHN KELIN J | 14 | 2013–2019 |
| CAPPELLANI ANNALISA | 12 | 2013–2019 |
| KIM SEIYON | 10 | 2014–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 45 | 2001–2021 |
| Austin, Texas, US | 21 | 2017–2021 |