Inventor
Jeffrey D. Gilbert
Inventor
Portland, OR, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing34%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10DInorganic electric semiconductor devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
C21DModifying the physical structure of ferrous metals2%
H05KPrinted circuits2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
10,078,592Resolving multi-core shared cache access conflicts20189,727,468'Resolving multi-core shared cache access conflicts'20179,501,129'Dynamically adjusting power of non-core processor circuitry including buffer circuitry'20168,914,650'Dynamically adjusting power of non-core processor circuitry including buffer circuitry'20148,407,432'Cache coherency sequencing implementation and adaptive LLC access priority control for CMP'20138,015,365'Reducing back invalidation transactions from a snoop filter'20117,915,732'Production of integrated circuit chip packages prohibiting formation of micro solder balls'20117,779,188'System and method to reduce memory latency in microprocessor systems connected with a bus'20107,714,366'CMOS transistor with a polysilicon gate electrode having varying grain size'20107,689,778'Preventing system snoop and cross-snoop conflicts'20107,647,476'Common analog interface for multiple processor cores'20107,581,068'Exclusive ownership snoop filter'20097,555,597'Direct cache access in multiple core processors'20097,484,044'Method and apparatus for joint cache coherency states in multi-interface caches'20097,228,387'Apparatus and method for an adaptive multiple line prefetcher'20077,124,229'Method and apparatus for improved performance for priority agent requests when symmetric agent bus parking is enabled'20067,008,852'Discontinuous dielectric interface for bipolar transistors'20066,939,771'Discontinuous dielectric interface for bipolar transistors'20056,893,948'Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size'20056,822,311'DC or AC electric field assisted anneal'20046,759,260'Metal oxide temperature monitor'20046,703,283'Discontinuous dielectric interface for bipolar transistors'20046,670,263'Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size'20036,660,664'Structure and method for formation of a blocked silicide resistor'20036,580,140'Metal oxide temperature monitor'20036,552,411'DC or AC electric field assisted anneal'20036,417,070'Method for forming a liner in a trench'20026,339,022'Method of annealing copper metallurgy'20026,271,100'Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2010Patents assigned to IBM (14)· patent assignee history
2001–2004Based in South Burlington, VT, US· patent location history
2002–2010Based in Burlington, VT, US· patent location history
2004–2006Based in Winooski, VT, US· patent location history
2006–2018Patents assigned to INTEL CORP (14)· patent assignee history
2006–2016Based in Portland, OR, US· patent location history
2010–2017Based in Hillsboro, OR, US· patent location history
2013–2017Patents assigned to GILBERT JEFFREY D (3)· patent assignee history
2013–2017Patents assigned to LIU YEN-CHENG (2)· patent assignee history
2013–2017Patents assigned to SISTLA KRISHNAKANTH V (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 14 | 2001–2010 |
| INTEL CORP | 14 | 2006–2018 |
| GILBERT JEFFREY Dself | 3 | 2013–2017 |
| LIU YEN-CHENG | 2 | 2013–2017 |
| SISTLA KRISHNAKANTH V | 2 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 9 | 2006–2016 |
| South Burlington, VT, US | 6 | 2001–2004 |
| Burlington, VT, US | 5 | 2002–2010 |
| Hillsboro, OR, US | 4 | 2010–2017 |
| Winooski, VT, US | 3 | 2004–2006 |