Inventor

Joseph Franklin Logan

Inventor

Raleigh, NC, US

Overview

1997–2015

Patent span

Electricity

Primary field (CPC H)

Patents· 39 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary

H04LTransmission of digital information, e.g. telegraphic communication57%

G06FElectric digital data processing36%

H03MCoding5%

G11CStatic stores2%

PatentTitleYear

9,041,572'Testing a digital-to-analog converter'2015 8,169,906'Controlling ATM traffic using bandwidth allocation technology'2012 8,170,024'Implementing pointer and stake model for frame alteration code in a network processor'2012 7,995,472'Flexible network processor scheduler and data flow'2011 7,904,617'Indicating data buffer by last bit flag'2011 7,643,511'Frame alteration logic for network processors'2010 7,627,701'Indicating last data buffer by last bit flag bit'2009 7,506,081'System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories'2009 7,483,429'Method and system for flexible network processor scheduler and data flow'2009 7,474,672'Frame alteration logic for network processors'2009 7,466,715'Flexible control block format for frame description and management'2008 7,412,546'System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position'2008 7,330,478'Method, apparatus, and computer program product for implementing pointer and stake model for frame alteration code in a network processor'2008 7,317,727'Method and systems for controlling ATM traffic using bandwidth allocation technology'2008 7,293,158'Systems and methods for implementing counters in a network processor with cost effective memory'2007 7,200,696'System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position'2007 7,149,212'Apparatus, method and limited set of messages to transmit data between scheduler and a network processor'2006 7,130,916'Linking frame data by inserting qualifiers in control blocks'2006 7,085,266'Apparatus, method and limited set of messages to transmit data between components of a network processor'2006 7,072,347'Assignment of packet descriptor field positions in a network processor'2006 6,996,650'Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus'2006 6,987,760'High speed network processor'2006 6,937,606'Data structures for efficient processing of IP fragmentation and reassembly'2005 6,910,092'Chip to chip interface for interconnecting chips'2005 6,836,480'Data structures for efficient processing of multicast transmissions'2004 6,757,795'Apparatus and method for efficiently sharing memory bandwidth in a network processor'2004 6,681,340'Efficient implementation of error correction code scheme'2004 6,658,546'Storing frame modification information in a bank in memory'2003 6,532,185'Distribution of bank accesses in a multiple bank DRAM used as a data buffer'2003 6,338,102'Efficient data transfer mechanism for input/output devices having a device driver generating a descriptor queue and monitoring a status queue'2002 6,334,162'Efficient data transfer mechanism for input/out devices having a device driver generating a descriptor queue and monitoring a status queue'2001 6,272,564'Efficient data transfer mechanism for input/output devices'2001 6,185,207'Communication system having a local area network adapter for selectively deleting information and method therefor'2001 6,163,820'Efficient data transfer mechanism for input/output devices'2000 6,073,181'Multi-buffer error detection for an open data-link interface LAN adapter'2000 6,049,842'Efficient data transfer mechanism for input/output devices'2000 5,905,913'System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor'1999 5,737,524'Add-in board with programmable configuration registers for use in PCI bus computers'1998 5,608,876'Add-in board with enable-disable expansion ROM for PCI bus computers'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2015Patents assigned to IBM (38)· patent assignee history

1997–2015Based in Raleigh, NC, US· patent location history

2003–2004Patents assigned to CIT ALCATEL (2)· patent assignee history

2008–2012Based in Apex, NC, US· patent location history

2012Patents assigned to DROZ PATRICK (1)· patent assignee history

2012Patents assigned to ILIADIS ILIAS (1)· patent assignee history

2012Patents assigned to IMMING KERRY CHRISTOPHER (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	38	1997–2015
CIT ALCATEL	2	2003–2004
DROZ PATRICK	1	2012
ILIADIS ILIAS	1	2012
IMMING KERRY CHRISTOPHER	1	2012

Locations

Location	Patents	Span
Raleigh, NC, US	37	1997–2015
Apex, NC, US	2	2008–2012