LexDanaLexDanabeta
Inventor

Vishal Sarin

Inventor
Cupertino, CA, US

Overview

166→
Patents
1998–2021
Patent span
Physics
Primary field (CPC G)

Patents· 166 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores76%
G06FElectric digital data processing13%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%
H10DInorganic electric semiconductor devices2%
H03FAmplifiers1%
H03MCoding1%
G05FSystems for regulating electric or magnetic variables1%
H01LSemiconductor devices1%
H03GControl of amplification1%
PatentTitleYear
10,984,864Methods and apparatus for pattern matching in a memory containing sets of memory elements202110,770,145Two-part programming methods202010,622,072Methods and apparatus for pattern matching having memory cell pairs coupled in series and coupled in parallel202010,249,365Two-part programming methods201910,141,055Methods and apparatus for pattern matching using redundant memory elements20189,875,799Methods for pattern matching using multiple cell pairs20189,858,991'Two-part programming methods'20189,646,683'Memory apparatus, systems, and methods'20179,520,183'Threshold voltage compensation in a memory'20169,502,101'Two-part programming methods'20169,471,425'Data conditioning to improve flash memory reliability'20169,423,969'Sensing operations in a memory device'20169,349,474'Apparatuses and methods for limiting string current in a memory'20169,240,240'Apparatus having indications of memory cell density and methods of their determination and use'20169,236,146'Single check memory devices and methods'20169,197,251'Method and apparatus for reading data from non-volatile memory'20159,196,370'Reducing noise in semiconductor devices'20159,177,651'Programming methods and memories'20159,165,681'Applying a voltage-delay correction to a non-defective memory block that replaces a defective memory block based on the actual location of the non-defective memory block'20159,158,612'Refresh of non-volatile memory cells based on fatigue conditions'20159,147,476'Programming methods and memories'20159,123,423'Programming operations in a memory device'20159,093,162'Sensing memory cells'20159,087,594'Memory apparatus, systems, and methods'20159,087,600'Two-part programming methods'20159,030,870'Threshold voltage compensation in a multilevel memory'20159,025,388'Method for kink compensation in a memory'20158,995,182'Coarse and fine programming in a solid state memory'20158,976,582'Analog sensing of memory cells in a solid-state memory device'20158,953,374'Programming based on controller performance requirements'20158,787,103'Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device'20148,773,912'Soft landing for desired program threshold voltage'20148,762,629'Data conditioning to improve flash memory reliability'20148,737,127'Memory controllers to output data signals of a number of bits and to receive data signals of a different number of bits'20148,719,680'Method and apparatus for reading data from non-volatile memory'20148,719,665'Programming error correction code into a solid state memory device with varying bits per cell'20148,713,246'Memory device program window adjustment'20148,711,616'Single check memory devices and methods'20148,705,299'Replacing defective memory blocks in response to external addresses'20148,707,112'Refresh of non-volatile memory cells based on fatigue conditions'20148,693,246'Memory controller self-calibration for removing systemic influence'20148,687,430'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20148,687,431'Programming methods and memories'20148,674,749'Fast start charge pump for voltage regulators'20148,644,070'Cell deterioration warning apparatus and method'20148,611,149'Programming based on controller performance requirements'20138,611,156'Sensing operations in a memory device'20138,582,357'Reducing effects of program disturb in a memory device'20138,578,244'Programming error correction code into a solid state memory device with varying bits per cell'20138,565,024'Sensing memory cells'20138,553,461'Method for kink compensation in a memory'20138,526,243'Configurable digital and analog input/output interface in a memory device'20138,499,229'Method and apparatus for reading data from flash memory'20138,497,667'Fast voltage regulators for charge pumps'20138,488,385'Reducing noise in semiconductor devices'20138,467,250'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20138,446,787'Replacing defective memory blocks in response to external addresses'20138,441,858'Apparatus having a string of memory cells'20138,422,312'Systems and methods for erasing a memory'20138,422,310'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20138,400,826'Coarse and fine programming in a solid state memory'20138,391,080'Erase voltage reduction in a non-volatile memory device'20138,385,121'Memory adapted to program a number of bits to a memory cell and read a different number of bits from the memory cell'20138,379,446'Memory controller self-calibration for removing systemic influence'20138,363,473'Analog read and write paths in a solid state memory device'20138,355,278'Reducing effects of program disturb in a memory device'20138,355,283'Sensing of memory cells in NAND flash'20138,307,152'Memory device program window adjustment'20128,295,109'Replacing defective columns of memory cells in response to external addresses'20128,289,776'Expanded programming window for non-volatile multilevel memory cells'20128,291,271'Programming error correction code into a solid state memory device with varying bits per cell'20128,281,061'Data conditioning to improve flash memory reliability'20128,274,823'Methods and apparatus utilizing expected coupling effect in the programming of memory cells'20128,274,833'Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device'20128,274,835'Mitigation of runaway programming of a memory device'20128,259,491'Coarse and fine programming in a solid state memory'20128,254,182'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20128,254,180'Methods of operating memories including characterizing memory cell signal lines'20128,243,523'Sensing operations in a memory device'20128,243,521'Method for kink compensation in a memory'20128,243,513'Non-volatile multilevel memory cells with data read of reference cells'20128,223,551'Soft landing for desired program threshold voltage'20128,213,233'Reduction of quick charge loss effect in a memory device'20128,203,886'Memory device reference cell programming method and apparatus'20128,174,919'Apparatus and method for increasing data line noise tolerance'20128,169,832'Methods of erase verification for a flash memory device'20128,125,831'Sensing against a reference cell'20128,127,091'Programming memory cells with additional data for increased threshold voltage resolution'20128,117,375'Memory device program window adjustment'20128,111,550'M+N bit programming and M+L bit read for M bit memory cells'20128,107,296'Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device'20128,102,706'Programming a memory with varying bits per cell'20128,103,940'Programming error correction code into a solid state memory device with varying bits per cell'20128,098,530'Systems and methods for erasing a memory'20128,089,805'Two-part programming methods and memories'20128,085,596'Reducing noise in semiconductor devices'20118,072,812'Sensing of memory cells in NAND flash'20118,068,366'Analog read and write paths in a solid state memory device'20118,067,931'Fast voltage regulators for charge pumps'20118,064,267'Erase voltage reduction in a non-volatile memory device'20118,060,798'Refresh of non-volatile memory cells based on fatigue conditions'20118,031,529'Memory cell threshold voltage drift estimation methods and apparatus'20118,027,200'Reduction of quick charge loss effect in a memory device'20118,023,324'Memory controller self-calibration for removing systemic influence'20118,023,334'Program window adjust for memory cell signal line delay'20118,023,332'Cell deterioration warning apparatus and method'20118,006,166'Programming error correction code into a solid state memory device with varying bits per cell'20118,004,887'Configurable digital and analog input/output interface in a memory device'20117,995,400'Reducing effects of program disturb in a memory device'20117,995,412'Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device'20117,957,196'Method of programming memory cells of series strings of memory cells'20117,948,802'Sensing memory cells'20117,944,755'Erase verify in memory devices'20117,939,892'Test circuit and method for multilevel cell flash memory'20117,936,599'Coarse and fine programming in a solid state memory'20117,916,536'Programming based on controller performance requirements'20117,907,444'Memory device reference cell programming method and apparatus'20117,898,885'Analog sensing of memory cells in a solid state memory device'20117,881,134'Replacing defective columns of memory cells in response to external addresses'20117,872,912'M+N bit programming and M+L bit read for M bit memory cells'20117,872,911'Non-volatile multilevel memory cells with data read of reference cells'20117,868,604'Fast voltage regulators for charge pumps'20117,864,589'Mitigation of runaway programming of a memory device'20117,864,584'Expanded programming window for non-volatile multilevel memory cells'20117,843,725'M+L bit read column architecture for M bit memory cells'20107,843,726'Sensing against a reference cell'20107,835,190'Methods of erase verification for a flash memory device'20107,831,872'Test circuit and method for multilevel cell flash memory'20107,830,718'Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device'20107,826,290'Apparatus and method for increasing data line noise tolerance'20107,817,467'Memory controller self-calibration for removing systemic influence'20107,787,307'Memory cell shift estimation method and apparatus'20107,782,674'Sensing of memory cells in NAND flash'20107,768,832'Analog read and write paths in a solid state memory device'20107,751,245'Programming sequence in NAND memory'20107,751,253'Analog sensing of memory cells with a source follower driver in a semiconductor memory device'20107,746,691'Methods and apparatus utilizing predicted coupling effect in the programming of non-volatile memory'20107,737,765'Fast start charge pump for voltage regulators'20107,729,150'High-speed and low-power differential non-volatile content addressable memory cell and array'20107,728,563'Fast voltage regulators for charge pumps'20107,729,167'Programming a memory with varying bits per cell'20107,663,926'Cell deterioration warning apparatus and method'20107,661,041'Test circuit and method for multilevel cell flash memory'20107,639,532'Non-equal threshold voltage ranges in MLC NAND'20097,633,798'M+N bit programming and M+L bit read for M bit memory cells'20097,619,933'Reducing effects of program disturb in a memory device'20097,596,037'Independent bi-directional margin control per level and independently expandable reference cell levels for flash memory sensing'20097,577,036'Non-volatile multilevel memory cells with data read of reference cells'20097,460,398'Programming a memory with varying bits per cell'20087,436,258'Multi-operational amplifier system'20087,423,895'High-speed and low-power differential non-volatile content addressable memory cell and array'20087,362,084'Fast voltage regulators for charge pumps'20087,336,516'Unified multilevel memory systems and methods'20087,325,177'Test circuit and method for multilevel cell flash memory'20087,276,971'Multi-operational amplifier system'20077,236,054'Multi-operational amplifier system'20077,212,459'Unified multilevel cell memory'20077,196,921'High-speed and low-power differential non-volatile content addressable memory cell and array'20077,161,844'Method and apparatus for compensating for bitline leakage current'20077,019,998'Unified multilevel cell memory'20066,992,934'Read bitline inhibit method and apparatus for voltage mode sensing'20066,943,617'Low voltage CMOS bandgap reference'20056,748,484'Match resolution circuit for an associative memory'20046,081,603'Method and apparatus for automatic gain control using a linear limiter circuit with voltage controlled resistors as a variable element'20005,973,967'Page buffer having negative voltage level shifter'19995,798,967'Sensing scheme for non-volatile memories'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2008Based in Santa Clara, CA, US· patent location history
2005–2014Patents assigned to SILICON STORAGE TECH INC (24)· patent assignee history
2006–2018Based in Cupertino, CA, US· patent location history
2008–2021Patents assigned to MICRON TECHNOLOGY INC (135)· patent assignee history
2011–2016Patents assigned to SARIN VISHAL (67)· patent assignee history
2011–2016Patents assigned to ROOHPARVAR FRANKIE F (44)· patent assignee history
2011–2015Patents assigned to HOEI JUNG-SHENG (23)· patent assignee history
2013–2021Based in Saratoga, CA, US· patent location history
2016Based in Cuprertino, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC1352008–2021
SARIN VISHALself672011–2016
ROOHPARVAR FRANKIE F442011–2016
SILICON STORAGE TECH INC242005–2014
HOEI JUNG-SHENG232011–2015
Locations
LocationPatentsSpan
Cupertino, California, US1342006–2018
Saratoga, California, US232013–2021
Santa Clara, California, US81998–2008
Cuprertino, California, US12016