LexDanaLexDanabeta
Inventor

Syed M. Alam

Inventor
Austin, TX, US

Overview

88→
Patents
2007–2021
Patent span
Physics
Primary field (CPC G)

Patents· 88 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores51%
G06FElectric digital data processing25%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
H03MCoding4%
H10BElectronic memory devices3%
H01LSemiconductor devices2%
H10NElectric solid-state devices not otherwise provided for2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
H10DInorganic electric semiconductor devices1%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%
PatentTitleYear
10,923,170Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines202110,657,065Delayed write-back in memory202010,658,013Feed forward bias system for MTJ voltage control202010,650,899Delayed write-back in memory with calibration support202010,614,907Short detection and inversion202010,608,671ECC word configuration for system-level ECC compatibility202010,573,365Circuit for wordline autobooting in memory and method therefor202010,475,497Self-referenced sense amplifier with precharge201910,446,213Bitline control in differential magnetic memory201910,395,699Memory device with shared amplifier circuitry201910,304,511Dual-edge trigger asynchronous clock generation and related methods201910,269,405Write verify programming of a memory device201910,268,591Delayed write-back in memory201910,262,713Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines201910,256,840ECC word configuration for system-level ECC compatibility201910,249,364Word line overdrive in memory and method therefor201910,199,122Short detection and inversion201910,146,601Methods and devices for healing reset errors in a magnetic memory201810,141,039Burst length defined page size201810,114,700Memory device with page emulation mode201810,037,790Word line auto-booting in a spin-torque magnetic memery having local source lines201810,020,041Self-referenced sense amplifier with precharge20189,997,239Word line overdrive in memory and method therefor20189,990,300Delayed write-back in memory20189,972,373Self-referenced read with offset current in a memory20189,911,481'Selection circuit with autobooting for magnetic memory and methods therefor'20189,881,695'Short detection and inversion'20189,870,812'Memory system with timing overlap mode for activate and precharge operations'20189,847,116Circuit and method for controlling MRAM cell bias voltages20179,740,431'Memory controller and method for interleaving DRAM and MRAM accesses'20179,734,884'Method for writing to a magnetic tunnel junction device'20179,697,879'Memory device with shared read/write circuitry'20179,697,880'Self-referenced read with offset current in a memory'20179,691,442'Memory device with reduced on-chip noise'20179,679,627'Write verify programming of a memory device'20179,601,175'Word line auto-booting in a spin-torque magnetic memory having local source lines'20179,583,169'Boosted supply voltage generator and method therefore'20179,575,125'Memory device with reduced test time'20179,569,640'Tamper detection and response in a memory device'20179,552,849'Memory device with timing overlap mode and precharge timing circuit'20179,552,863'Memory device with sampled resistance controlled write voltages'20179,543,041'Configuration and testing for magnetoresistive memory to ensure long term continuous operation'20179,542,989'Circuit and method for controlling MRAM cell bias voltages'20179,529,726'Memory device with page emulation mode'20169,530,476'Memory device with shared read/write circuitry'20169,529,672'ECC word configuration for system-level ECC compatibility'20169,502,093'Method of writing to a spin torque magnetic random access memory'20169,502,089'Short detection and inversion'20169,454,432'Method of reading and writing to a spin torque magnetic random access memory with error correcting code'20169,443,113'Response to tamper detection in a memory device'20169,418,001'Memory controller and method for interleaving DRAM and MRAM accesses'20169,401,195'Self-referenced sense amplifier for spin-torque MRAM'20169,378,796'Method for writing to a magnetic tunnel junction device'20169,378,798'Method of writing to a spin torque magnetic random access memory'20169,368,181'Circuit and method for accessing a bit cell in a spin-torque MRAM'20169,361,964'Boosted supply voltage generator for a memory device and method therefore'20169,336,848'Memory device with differential bit cells'20169,336,849'Memory device with shared read/write circuitry'20169,311,980'Word line supply voltage generator for a memory device and method therefore'20169,299,411'Hybrid read scheme for spin torque MRAM'20169,286,218'Word line auto-booting in a spin-torque magnetic memory having local source lines'20169,245,611'Method of writing to a spin torque magnetic random access memory'20169,230,633'Memory device with timing overlap mode'20169,230,632'Word line driver circuit'20169,218,865'Self-referenced sense amplifier for spin torque MRAM'20159,218,509'Response to tamper detection in a memory device'20159,196,342'Circuit and method for spin-torque MRAM bit line and source line voltage regulation'20159,183,912'Circuit and method for controlling MRAM cell bias voltages'20159,183,911'Hybrid read scheme for spin torque MRAM'20159,135,970'Tamper detection and response in a memory device'20159,135,965'Memory controller and method for interleaving DRAM and MRAM accesses'20159,111,622'Self referencing sense amplifier for spin torque MRAM'20159,112,536'Method of reading and writing to a spin torque magnetic random access memory with error correcting code'20159,047,965'Circuit and method for spin-torque MRAM bit line and source line voltage regulation'20159,047,969'Method of writing to a spin torque magnetic random access memory'20159,047,967'Data-masked analog and digital read for resistive memories'20159,019,794'Memory device with reduced on-chip noise'20159,007,811'Word line driver circuit'20158,984,379'MRAM field disturb detection and recovery'20158,976,610'Memory device with timing overlap mode'20158,929,132'Write driver circuit and method for writing to a spin-torque MRAM'20158,923,041'Self-referenced sense amplifier for spin torque MRAM'20148,817,530'Data-masked analog and digital read for resistive memories'20148,811,071'Method of writing to a spin torque magnetic random access memory'20147,723,207'Three dimensional integrated circuit and method of design'20107,715,227'Programmable ROM using two bonded strata'20107,358,616'Semiconductor stacked die/wafer configuration and packaging and method thereof'20087,312,487'Three dimensional integrated circuit'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2010Based in Cambridge, MA, US· patent location history
2008–2010Patents assigned to FREESCALE SEMICONDUCTOR INC (2)· patent assignee history
2008–2021Based in Austin, TX, US· patent location history
2014–2021Patents assigned to EVERSPIN TECHNOLOGIES INC (84)· patent assignee history
2014–2015Patents assigned to ALAM SYED M (5)· patent assignee history
2014–2015Patents assigned to THOMAS ANDRE (5)· patent assignee history
2014–2015Patents assigned to CROFT MATTHEW R (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
EVERSPIN TECHNOLOGIES INC842014–2021
ALAM SYED Mself52014–2015
THOMAS ANDRE52014–2015
CROFT MATTHEW R32014–2015
FREESCALE SEMICONDUCTOR INC22008–2010
Locations
LocationPatentsSpan
Austin, Texas, US862008–2021
Cambridge, Massachusetts, US22007–2010