Inventor
YU-TING LIN
Inventor
TW
Overview
Patents· 58 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10DInorganic electric semiconductor devices12%
H10BElectronic memory devices10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
G01RMeasuring electric variables9%
H01GCapacitors3%
C23CCoating metallic material2%
G11CStatic stores2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
PatentTitleYear
12,571,832Inspection apparatus and method202612,553,814Biosensor using particle motion202612,553,939Interconnect structures in integrated circuit chips202612,557,568Conductive feature formation and structure202612,532,720Forming openings through carrier substrate of IC package assembly for fault identification202612,512,324Selective formation of titanium silicide and titanium nitride by hydrogen gas control202512,501,611Integrated circuit device202512,482,657Method of manufacturing semiconductor structure using multi-layer hard mask202512,453,079Method of manufacturing semiconductor structure comprising edge word line and central word line202512,446,255Semiconductor structure with source/drain multi-layer structure and method for forming the same202512,403,360Intelligent exercise intensity assessing system and assessing method thereof202512,320,493Flexible warning light202512,313,675Method and device for wafer-level testing202512,317,482Semiconductor structure and method of manufacturing the same including buried word lines of different widths202512,300,729Low resistant contact method and structure202512,270,852Method and system for wafer-level testing202512,265,119Repackaging IC chip for fault identification202512,245,421Semiconductor device with bit line contacts of different pitches202512,230,450Semiconductor structure202512,219,709Forming trench in IC chip through multiple trench formation and deposition processes202512,198,991Test structure for use in dynamic random access memory and manufacturing method thereof202512,191,199Contact metallization process202512,158,227Flow control structure of water hose joint202412,148,132Image calibration method and image calibration apparatus202412,087,575Conductive feature formation and structure202412,066,484Method and device for wafer-level testing202412,025,655Method and system for wafer-level testing202411,990,550Semiconductor structure with source/drain multi-layer structure and method for forming the same202411,972,951Selective formation of titanium silicide and titanium nitride by hydrogen gas control202411,950,408Semiconductor structure and method of manufacturing the same202411,942,277Method of manufacturing semiconductor structure and semiconductor structure202411,934,838Storing EFI variables in a BMC using an API202411,903,186Method for manufacturing semiconductor device with bit line contacts of different pitches202411,876,142PN junction and preparation method and use thereof2024D1009244Ceiling fan202311,835,265Apparatus combining solar tracker and dual heat source collector202311,754,621Method and device for wafer-level testing202311,705,833Motor controller, motor control method and computer program product for vehicle assist control202311,683,928Semiconductor device with single step height202311,630,149Method and system for wafer-level testing202311,588,011Method of capacitance structure manufacturing202311,569,228Semiconductor structure and method of manufacturing the same202311,527,655Semiconductor structure with source/drain multi-layer structure and method for forming the same202211,526,073Pellicle and method of manufacturing same202211,520,735Data migration to a cloud computing system202211,472,435Trajectory determination method for a vehicle202211,448,692Method and device for wafer-level testing202211,437,383Method for fabricating dynamic random access memory devices202211,411,006Manufacturing method of memory structure202211,404,533Capacitance structure and manufacturing method thereof202211,374,009Integrated circuit device and manufacturing method thereof202211,340,525Pellicle and method of manufacturing same202211,309,316Semiconductor device with single step height and method for fabricating the same202211,295,956Selective formation of titanium silicide and titanium nitride by hydrogen gas control202211,289,492Semiconductor structure and method of manufacturing thereof202211,264,391Semiconductor structure and manufacturing method thereof202211,232,945Conductive feature formation and structure202211,173,107Uses of 2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Based in TW· patent location history
2022–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (24)· patent assignee history
2022–2025Patents assigned to NANYA TECHNOLOGY CORP (20)· patent assignee history
2022Patents assigned to AUTOMOTIVE RES & TESTING CT (1)· patent assignee history
2022Based in US· patent location history
2023–2024Patents assigned to LIN YU TING (2)· patent assignee history
2024Patents assigned to ALTEK SEMICONDUCTOR CORP (1)· patent assignee history
2026Based in NL· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 24 | 2022–2026 |
| NANYA TECHNOLOGY CORP | 20 | 2022–2025 |
| LIN YU TINGself | 2 | 2023–2024 |
| ALTEK SEMICONDUCTOR CORP | 1 | 2024 |
| AUTOMOTIVE RES & TESTING CT | 1 | 2022 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 56 | 2021–2026 |
| NL | 1 | 2026 |
| US | 1 | 2022 |