Inventor
Raghunandan Makaram
Inventor
Northborough, MA, US
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing42%
H04LTransmission of digital information, e.g. telegraphic communication25%
G11CStatic stores21%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
H04WWireless communication networks1%
PatentTitleYear
11,070,527Securing platform link with encryption202111,048,800Composable trustworthy execution environments202111,030,120Host-convertible secure enclaves in memory that leverage multi-key total memory encryption with integrity202111,023,233Methods, apparatus, and instructions for user level thread suspension202110,972,277Confidential verification of FPGA code202110,922,241Supporting secure memory intent202110,877,549Configuring power management functionality in a processor202010,871,983Process-based multi-key total memory encryption202010,841,288Cloud key management for AFU security202010,671,740Supporting configurable security levels for memory address ranges202010,628,315Secure memory repartitioning technologies202010,581,590Flexible architecture and instruction for advanced encryption standard (AES)202010,554,386Flexible architecture and instruction for advanced encryption standard (AES)202010,318,440Mapping security policy group registers201910,313,107Flexible architecture and instruction for advanced encryption standard (AES)201910,291,394Flexible architecture and instruction for advanced encryption standard (AES)201910,282,306Supporting secure memory intent201910,270,589Flexible architecture and instruction for advanced encryption standard (AES)201910,263,769Flexible architecture and instruction for advanced encryption standard (AES)201910,256,972Flexible architecture and instruction for advanced encryption standard (AES)201910,256,971Flexible architecture and instruction for advanced encryption standard (AES)201910,230,528Tree-less integrity and replay memory protection for trusted execution environment201910,203,741Configuring power management functionality in a processor201910,191,532Configuring power management functionality in a processor201910,185,842Cache and data organization for memory protection201910,187,201Flexible architecture and instruction for advanced encryption standard (AES)201910,181,945Flexible architecture and instruction for advanced encryption standard (AES)201910,171,232Flexible architecture and instruction for advanced encryption standard (AES)201910,171,231Flexible architecture and instruction for advanced encryption standard (AES)201910,164,769Flexible architecture and instruction for advanced encryption standard (AES)201810,158,478Flexible architecture and instruction for advanced encryption standard (AES)201810,031,861Protect non-memory encryption engine (non-mee) metadata in trusted execution environment20189,959,418Supporting configurable security levels for memory address ranges20189,875,189Supporting secure memory intent20189,798,641'Method to increase cloud availability and silicon isolation using secure enclaves'20179,767,044'Secure memory repartitioning'20179,760,155'Configuring power management functionality in a processor'20179,654,282'Flexible architecture and instruction for advanced encryption standard (AES)'20179,654,281'Flexible architecture and instruction for advanced encryption standard (AES)'20179,647,831'Flexible architecture and instruction for advanced encryption standard (AES)'20179,641,319'Flexible architecture and instruction for advanced encryption standard (AES)'20179,641,320'Flexible architecture and instruction for advanced encryption standard (AES)'20179,634,829'Flexible architecture and instruction for advanced encryption standard (AES)'20179,634,830'Flexible architecture and instruction for advanced encryption standard (AES)'20179,634,828'Flexible architecture and instruction for advanced encryption standard (AES)'20179,448,950'Using authenticated manifests to enable external certification of multi-processor platforms'20169,235,244'Configuring power management functionality in a processor'20168,984,313'Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2021Patents assigned to INTEL CORP (48)· patent assignee history
2015Patents assigned to BHANDARU MALINI K (1)· patent assignee history
2015Patents assigned to BOBHOLZ SCOTT P (1)· patent assignee history
2015Patents assigned to DEHAEMER ERIC J (1)· patent assignee history
2015Patents assigned to GARG VIVEK (1)· patent assignee history
2015–2021Based in Northborough, MA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 48 | 2015–2021 |
| BHANDARU MALINI K | 1 | 2015 |
| BOBHOLZ SCOTT P | 1 | 2015 |
| DEHAEMER ERIC J | 1 | 2015 |
| GARG VIVEK | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Northborough, Massachusetts, US | 48 | 2015–2021 |