Inventor

Hemanth Jagannathan

Inventor

Niskayuna, NY, US

Overview

2004–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 186 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices36%

H01LSemiconductor devices32%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

H10BElectronic memory devices2%

B82YSpecific uses or applications of nanostructures1%

G06KGraphical data reading1%

H04LTransmission of digital information, e.g. telegraphic communication0%

B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form0%

C23CCoating metallic material0%

PatentTitleYear

11,121,209Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor2021 11,094,801Oxide isolated fin-type field-effect transistors2021 11,088,033Low resistance source-drain contacts using high temperature silicides2021 11,062,956Low resistance source-drain contacts using high temperature silicides2021 10,935,943Combining home automation and UAV technology2021 10,833,173Low-resistance top contact on VTFET2020 10,832,969Single-fin CMOS transistors with embedded and cladded source/drain structures2020 10,832,975Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement2020 10,833,148Leakage current reduction in stacked metal-insulator-metal capacitors2020 10,833,172Gate stack reliability in vertical transport field effect transistors2020 10,833,150Fast recrystallization of hafnium or zirconium based oxides in insulator-metal structures2020 10,825,916Vertical transport field-effect transistor including dual layer top spacer2020 10,825,740Low resistance source-drain contacts using high temperature silicides2020 10,790,199Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering2020 10,777,659Self-aligned bottom source/drain epitaxial growth in vertical field effect transistors2020 10,749,012Formation of self-aligned bottom spacer for vertical transistors2020 10,741,652Wrap-around-contact structure for top source/drain in vertical FETs2020 10,741,663Encapsulation layer for vertical transport field-effect transistor gate stack2020 10,734,475Stacked MIM capacitors with self-aligned contact to reduce via enclosure2020 10,714,399Gate-last process for vertical transport field-effect transistor2020 10,685,888Low resistance source-drain contacts using high temperature silicides2020 10,685,876Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability2020 10,680,083Oxide isolated fin-type field-effect transistors2020 10,672,670Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages2020 10,672,905Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts2020 10,658,299Replacement metal gate processes for vertical transport field-effect transistor2020 10,651,266Efficient metal-insulator-metal capacitor2020 10,636,792Structure and method for multiple threshold voltage definition in advanced CMOS device technology2020 10,615,082VFET metal gate patterning for vertical transport field effect transistor2020 10,615,043Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device2020 10,615,083Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device2020 10,607,990Fabrication of field effect transistors with different threshold voltages through modified channel interfaces2020 10,593,797Vertical transport field effect transistor structure with self-aligned top junction through early top source/drain epitaxy2020 10,580,881Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices2020 10,573,565Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments2020 10,573,746VTFET devices utilizing low temperature selective epitaxy2020 10,559,672Vertical transport field-effect transistor including dual layer top spacer2020 10,559,671Vertical transport field-effect transistor including air-gap top spacer2020 10,546,787Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device2020 10,541,239Semiconductor device and method of forming the semiconductor device2020 10,535,773FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation2020 10,529,573Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device2020 10,504,997Silicon-germanium Fin structure having silicon-rich outer surface2019 10,483,361Wrap-around-contact structure for top source/drain in vertical FETs2019 10,461,172Vertical transistors having improved gate length control using uniformly deposited spacers2019 10,439,043Formation of self-aligned bottom spacer for vertical transistors2019 10,431,502Maskless epitaxial growth of phosphorus-doped Si and boron-doped SiGe (Ge) for advanced source/drain contact2019 10,396,076Structure and method for multiple threshold voltage definition in advanced CMOS device technology2019 10,395,079Simplified gate stack process to improve dual channel CMOS performance2019 10,395,080Simplified gate stack process to improve dual channel CMOS performance2019 10,396,146Leakage current reduction in stacked metal-insulator-metal capacitors2019 10,395,989Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETs2019 10,381,479Interface charge reduction for SiGe surface2019 10,381,433Leakage current reduction in stacked metal-insulator-metal capacitors2019 10,373,912Replacement metal gate processes for vertical transport field-effect transistor2019 10,361,130Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering2019 10,361,129Self-aligned double patterning formed fincut2019 10,340,355Method of forming a dual metal interconnect structure2019 10,319,833Vertical transport field-effect transistor including air-gap top spacer2019 10,312,147Multi-layer work function metal gates with similar gate thickness to achieve multi-VT for VFETs2019 10,304,746Complementary metal oxide semiconductor replacement gate high-K metal gate devices with work function adjustments2019 10,304,938Maskless method to reduce source-drain contact resistance in CMOS devices2019 10,304,831Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins2019 10,297,671Uniform threshold voltage for nanosheet devices2019 10,297,598Formation of full metal gate to suppress interficial layer growth2019 10,290,700Multilayer dielectric for metal-insulator-metal capacitor (MIMCAP) capacitance and leakage improvement2019 10,283,620Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices2019 10,276,687Formation of self-aligned bottom spacer for vertical transistors2019 10,256,289Efficient metal-insulator-metal capacitor fabrication2019 10,256,159Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device2019 10,256,161Dual work function CMOS devices2019 10,249,758FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation2019 10,249,540Dual channel CMOS having common gate stacks2019 10,236,219VFET metal gate patterning for vertical transport field effect transistor2019 10,229,856Dual channel CMOS having common gate stacks2019 10,229,975Fabrication of silicon-germanium fin structure having silicon-rich outer surface2019 10,229,986Vertical transport field-effect transistor including dual layer top spacer2019 10,170,316Controlling threshold voltage in nanosheet transistors2019 10,147,680Method to reduce variability in contact resistance2018 10,128,372Bottom contact resistance reduction on VFET2018 10,096,713FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation2018 10,090,378Efficient metal-insulator-metal capacitor2018 10,084,055Uniform threshold voltage for nanosheet devices2018 10,084,082Bottom contact resistance reduction on VFET2018 10,079,233Semiconductor device and method of forming the semiconductor device2018 10,056,484VTFET devices utilizing low temperature selective epitaxy2018 10,020,359Leakage current reduction in stacked metal-insulator-metal capacitors2018 10,008,386Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device2018 10,002,791Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS2018 9,984,263Simplified gate stack process to improve dual channel CMOS performance2018 9,978,748Method of cutting fins to create diffusion breaks for finFETs2018 9,960,272Bottom contact resistance reduction on VFET2018 9,954,106III-V fin on insulator2018 9,941,371Selective thickening of pFET dielectric2018 9,917,089'III-V semiconductor CMOS FinFET device'2018 9,881,797'Replacement gate electrode with multi-thickness conductive metallic nitride layers'2018 9,876,091Divot-free planarization dielectric layer for replacement gate2018 9,865,703'High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process'2018 9,865,730'VTFET devices utilizing low temperature selective epitaxy'2018 9,837,357Method to reduce variability in contact resistance2017 9,824,930'Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme'2017 9,818,616'Controlling threshold voltage in nanosheet transistors'2017 9,773,875'Fabrication of silicon-germanium fin structure having silicon-rich outer surface'2017 9,761,722'Isolation of bulk FET devices with embedded stressors'2017 9,761,655'Stacked planar capacitors with scaled EOT'2017 9,754,967'Structure for integration of an III-V compound semiconductor on SOI'2017 9,741,822'Simplified gate stack process to improve dual channel CMOS performance'2017 9,741,812'Dual metal interconnect structure'2017 9,721,842'Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme'2017 9,722,038'Metal cap protection layer for gate and contact metallization'2017 9,666,486'Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate'2017 9,659,938'Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins'2017 9,653,537'Controlling threshold voltage in nanosheet transistors'2017 9,627,214'Stratified gate dielectric stack for gate dielectric leakage reduction'2017 9,627,510'Structure and method for replacement gate integration with self-aligned contacts'2017 9,595,449'Silicon-germanium semiconductor devices and method of making'2017 9,589,845'Fin cut enabling single diffusion breaks'2017 9,583,489'Solid state diffusion doping for bulk finFET devices'2017 9,577,062'Dual metal gate electrode for reducing threshold voltage'2017 9,570,569'Selective thickening of PFET dielectric'2017 9,548,319'Structure for integration of an III-V compound semiconductor on SOI'2017 9,530,651'Replacement metal gate finFET'2016 9,514,948'Stratified gate dielectric stack for gate dielectric leakage reduction'2016 9,515,073'III-V semiconductor CMOS FinFET device'2016 9,496,183'Selective thickening of pFET dielectric'2016 9,490,255'Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments'2016 9,484,439'III-V fin on insulator'2016 9,472,407'Replacement metal gate FinFET'2016 9,472,408'Nitridation on HDP oxide before high-k deposition to prevent oxygen ingress'2016 9,472,419'Method of patterning dopant films in high-K dielectrics in a soft mask integration scheme'2016 9,437,436'Replacement metal gate FinFET'2016 9,425,080'Non-volatile memory device employing semiconductor nanoparticles'2016 9,412,596'Nitridation on HDP oxide before high-k deposition to prevent oxygen ingress'2016 9,406,679'Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate'2016 9,397,197'Forming wrap-around silicide contact on finFET'2016 9,385,207'Stratified gate dielectric stack for gate dielectric leakage reduction'2016 9,356,121'Divot-free planarization dielectric layer for replacement gate'2016 9,330,938'Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme'2016 9,318,581'Forming wrap-around silicide contact on finFET'2016 9,299,706'Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins'2016 9,202,698'Replacement gate electrode with multi-thickness conductive metallic nitride layers'2015 9,190,409'Replacement metal gate transistor with controlled threshold voltage'2015 9,153,447'Replacement metal gate FinFET'2015 9,093,376'Replacement metal gate FinFET'2015 9,093,558'Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate'2015 9,064,744'Structure and method to realize conformal doping in deep trench applications'2015 9,059,314'Structure and method to obtain EOT scaled dielectric stacks'2015 9,054,127'Robust replacement gate integration'2015 9,006,094'Stratified gate dielectric stack for gate dielectric leakage reduction'2015 9,006,816'Memory device having multiple dielectric gate stacks and related methods'2015 8,994,006'Non-volatile memory device employing semiconductor nanoparticles'2015 8,906,793'Borderless contact for an aluminum-containing gate'2014 8,901,667'High performance non-planar semiconductor devices with metal filled inter-fin gaps'2014 8,901,670'Semiconductor device including multiple metal semiconductor alloy region and a gate structure covered by a continuous encapsulating layer'2014 8,900,936'FinFET device having reduce capacitance, access resistance, and contact resistance'2014 8,890,255'Structure and method for stress latching in non-planar semiconductor devices'2014 8,877,615'Methods of manufacturing finFET devices'2014 8,860,123'Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods'2014 8,847,323'finFET devices'2014 8,835,237'Robust replacement gate integration'2014 8,835,232'Low external resistance ETSOI transistors'2014 8,835,260'Control of threshold voltages in high-k metal gate stack and structures for CMOS devices'2014 8,790,991'Method and structure for shallow trench isolation to mitigate active shorts'2014 8,779,515'Semiconductor structure containing an aluminum-containing replacement gate electrode'2014 8,753,934'Structure and method to integrate embedded DRAM with FinFET'2014 8,748,991'Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices'2014 8,741,757'Replacement gate electrode with multi-thickness conductive metallic nitride layers'2014 8,722,548'Structures and techniques for atomic layer deposition'2014 8,679,941'Method to improve wet etch budget in FEOL integration'2014 8,680,629'Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices'2014 8,653,610'High performance non-planar semiconductor devices with metal filled inter-fin gaps'2014 8,614,486'Low resistance source and drain extensions for ETSOI'2013 8,541,275'Single metal gate CMOS integration by intermixing polarity specific capping layers'2013 8,486,778'Low resistance source and drain extensions for ETSOI'2013 8,421,139'Structure and method to integrate embedded DRAM with finfet'2013 8,394,684'Structure and method for stress latching in non-planar semiconductor devices'2013 8,368,146'FinFET devices'2013 8,309,447'Method for integrating multiple threshold voltage devices for CMOS'2012 8,304,836'Structure and method to obtain EOT scaled dielectric stacks'2012 8,274,116'Control of threshold voltages in high-k metal gate stack and structures for CMOS devices'2012 8,232,179'Method to improve wet etch budget in FEOL integration'2012 8,133,746'Method for semiconductor gate hardmask removal and decoupling of implants'2012 8,124,485'Molecular spacer layer for semiconductor oxide surface and high-K dielectric stack'2012 7,943,458'Methods for obtaining gate stacks with tunable threshold voltage and scaling'2011 7,855,105'Planar and non-planar CMOS devices with multiple tuned threshold voltages'2010 6,789,426'Microfluidic channels with integrated ultrasonic transducers for temperature measurement and method'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2021Patents assigned to IBM (183)· patent assignee history

2010–2020Based in Albany, NY, US· patent location history

2012–2015Patents assigned to JAGANNATHAN HEMANTH (31)· patent assignee history

2012–2015Patents assigned to HARAN BALASUBRAMANIAN S (7)· patent assignee history

2012–2015Patents assigned to NARAYANAN VIJAY (7)· patent assignee history

2012–2015Patents assigned to ANDO TAKASHI (6)· patent assignee history

2012–2019Based in Guilderland, NY, US· patent location history

2012–2015Based in Armonk, NY, US· patent location history

2016–2021Based in Niskayuna, NY, US· patent location history

2021Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	183	2010–2021
JAGANNATHAN HEMANTHself	31	2012–2015
HARAN BALASUBRAMANIAN S	7	2012–2015
NARAYANAN VIJAY	7	2012–2015
ANDO TAKASHI	6	2012–2015

Locations

Location	Patents	Span
Niskayuna, New York, US	119	2016–2021
Guilderland, New York, US	49	2012–2019
Albany, New York, US	13	2010–2020
Armonk, New York, US	2	2012–2015
San Jose, California, US	1	2021