Inventor
Srikanth B. Samavedam
Inventor
Fishkill, NY, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices48%
H01LSemiconductor devices24%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G11CStatic stores2%
B82YSpecific uses or applications of nanostructures1%
C30BSingle-crystal growth1%
H10BElectronic memory devices1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
11,127,818High voltage transistor with fin source/drain regions and trench gate structure202110,644,157Fin-type field effect transistors with uniform channel lengths and below-channel isolation on bulk semiconductor substrates and methods202010,483,172Transistor device structures with retrograde wells in CMOS applications201910,347,748Methods of forming source/drain regions on FinFET devices20199,966,313FinFET device and method of manufacturing20189,935,112SRAM cell having dual pass gate transistors and method of making the same20189,852,954Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures20179,576,952'Integrated circuits with varying gate structures and fabrication methods'20179,508,743'Dual three-dimensional and RF semiconductor devices using local SOI'20169,455,201'Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits'20169,437,740'Epitaxially forming a set of fins in a semiconductor device'20169,362,357'Blanket EPI super steep retrograde well formation without Si recess'20169,362,280'Semiconductor devices with different dielectric thicknesses'20169,362,180'Integrated circuit having multiple threshold voltages'20169,209,181'Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures'20159,196,548'Methods of using a trench salicide routing layer'20159,099,380'Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device'20159,099,492'Methods of forming replacement gate structures with a recessed channel'20159,099,525'Blanket EPI super steep retrograde well formation without Si recess'20159,040,404'Replacement metal gate structure for CMOS device'20159,034,737'Epitaxially forming a set of fins in a semiconductor device'20158,916,442'Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device'20148,809,178'Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents'20148,460,996'Semiconductor devices with different dielectric thicknesses'20138,178,401'Method for fabricating dual-metal gate device'20128,039,339'Separate layer formation in a semiconductor device'20118,012,821'Semiconductor embedded resistor generation'20118,003,454'CMOS process with optimized PMOS and NMOS transistor devices'20117,910,442'Process for making a semiconductor device using partial etching'20117,858,482'Method of forming a semiconductor device using stress memorization'20107,750,374'Process for forming an electronic device including a transistor having a metal gate electrode'20107,709,331'Dual gate oxide device integration'20107,683,439'Semiconductor device having a metal carbide gate with an electropositive element and a method of making the same'20107,666,730'Method for forming a dual metal gate structure'20107,655,550'Method of making metal gate transistors'20107,445,976'Method of forming a semiconductor device having an interlayer and structure therefor'20087,445,981'Method for forming a dual metal gate structure'20086,972,224'Method for fabricating dual-metal gate device'20056,897,095'Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode'20056,894,353'Capped dual metal gate transistors for CMOS process and method for making the same'20056,790,719'Process for forming dual metal gate structures'20046,514,808'Transistor having a high K dielectric and short gate length and method therefor'20036,475,841'Transistor with shaped gate electrode and method therefor'20026,423,632'Semiconductor device and a process for forming the same'20026,320,784'Memory cell and method for programming thereof'20016,039,803'Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000Based in Cambridge, MA, US· patent location history
2001–2003Patents assigned to MOTOROLA INC (4)· patent assignee history
2001–2016Based in Austin, TX, US· patent location history
2004–2016Patents assigned to FREESCALE SEMICONDUCTOR INC (18)· patent assignee history
2008–2019Based in Fishkill, NY, US· patent location history
2012–2016Patents assigned to SAMAVEDAM SRIKANTH B (3)· patent assignee history
2014–2020Patents assigned to GLOBALFOUNDRIES INC (21)· patent assignee history
2014–2015Patents assigned to SAMAVEDAM SRIKANTH (4)· patent assignee history
2015–2021Based in Cohoes, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 21 | 2014–2020 |
| FREESCALE SEMICONDUCTOR INC | 18 | 2004–2016 |
| MOTOROLA INC | 4 | 2001–2003 |
| SAMAVEDAM SRIKANTHself | 4 | 2014–2015 |
| SAMAVEDAM SRIKANTH Bself | 3 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fishkill, New York, US | 19 | 2008–2019 |
| Austin, Texas, US | 15 | 2001–2016 |
| Cohoes, New York, US | 11 | 2015–2021 |
| Cambridge, Massachusetts, US | 1 | 2000 |