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Inventor

Jay J. Nejedlo

Inventor
Wilsonville, OR, US

Overview

10→
Patents
2004–2019
Patent span
Physics
Primary field (CPC G)

Patents· 10 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing47%
G01RMeasuring electric variables33%
G11CStatic stores13%
H04LTransmission of digital information, e.g. telegraphic communication7%
PatentTitleYear
10,198,333Test, validation, and debug architecture20198,868,992'Robust memory link testing using memory controller'20147,590,504'Graphical user interface for creation of IBIST tests'20097,562,274'User data driven test control software application the requires no software maintenance'20097,536,267'Built-in self test for memory interconnect testing'20097,464,307'High performance serial bus testing methodology'20087,437,643'Automated BIST execution scheme for a link'20087,155,370'Reusable, built-in self-test methodology for computer systems'20067,047,458'Testing methodology and apparatus for interconnects'20066,826,100'Push button mode automatic pattern switching for interconnect built-in self test'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2019Patents assigned to INTEL CORP (8)· patent assignee history
2004–2019Based in Wilsonville, OR, US· patent location history
2009Patents assigned to ASSET INTERTECH INC (2)· patent assignee history
2014–2019Patents assigned to NEJEDLO JAY J (2)· patent assignee history
2014–2019Patents assigned to QUERBACH BRUCE (2)· patent assignee history
2014Patents assigned to ABRAHAM PHILIP (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP82004–2019
ASSET INTERTECH INC22009
NEJEDLO JAY Jself22014–2019
QUERBACH BRUCE22014–2019
ABRAHAM PHILIP12014
Locations
LocationPatentsSpan
Wilsonville, OR, US102004–2019