Inventor
Stephen H. Gunther
Inventor
Beaverton, OR, US
Overview
80→
Patents
1996–2021
Patent span
General tagging of new technological developments
Primary field (CPC Y)
Patents· 80 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing43%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use34%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications15%
G01KMeasuring temperature2%
F04DNon-positive-displacement pumps1%
G05FSystems for regulating electric or magnetic variables1%
G11BInformation storage based on relative movement between record carrier and transducer1%
G11CStatic stores1%
H02JElectric power networks1%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems1%
PatentTitleYear
10,963,028System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time202110,635,155Independent power control of processing cores202010,613,610Independent power control of processing cores202010,545,793Thread scheduling using processing engine information202010,534,419Independent power control of processing cores202010,372,197User level control of power management policies201910,345,884Mechanism to provide workload and configuration-aware deterministic performance for microprocessors201910,282,296Zeroing a cache line201910,139,882System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time201810,095,300Independent power control of processing cores20189,898,067'Method and apparatus to configure thermal design power in a microprocessor'20189,898,066'Method and apparatus to configure thermal design power in a microprocessor'20189,841,803'Independent power control of processing cores'20179,746,903'Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit'20179,671,854'Controlling configurable peak performance limits of a processor'20179,594,560'Estimating scalability value for a specific domain of a multicore processor based on active state residency of the domain, stall duration of the domain, memory bandwidth of the domain, and a plurality of coefficients based on a workload to execute on the domain'20179,575,543'Providing an inter-arrival access timer in a processor'20179,563,254'System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time'20179,535,487'User level control of power management policies'20179,444,328'Acoustic noise mitigation using periodicity disruption'20169,417,681'Mechanism to provide workload and configuration-aware deterministic performance for microprocessors'20169,405,345'Constraining processor operation based on power envelope information'20169,360,909'System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time'20169,268,393'Enforcing a power consumption duty cycle in a processor'20169,239,611'Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme'20169,235,252'Dynamic balancing of power across a plurality of processor domains according to power policy control bias'20169,189,046'Performing cross-domain thermal control in a processor'20159,170,624'User level control of power management policies'20159,164,565'Apparatus and method to manage energy usage of a processor'20159,141,167'Apparatus and method to manage energy usage of a processor'20159,134,788'Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit'20159,098,261'User level control of power management policies'20159,086,834'Controlling configurable peak performance limits of a processor'20159,081,577'Independent control of processor core retention states'20159,075,556'Controlling configurable peak performance limits of a processor'20159,063,727'Performing cross-domain thermal control in a processor'20159,052,901'Method, apparatus, and system for energy efficiency and energy conservation including configurable maximum processor current'20159,037,889'Apparatus and method for determining the number of execution cores to keep active in a processor'20159,037,885'Independent power control of processing cores'20159,037,840'Mechanism to provide workload and configuration-aware deterministic performance for microprocessors'20159,032,232'Instruction for enabling a processor wait state'20159,021,279'Independent power control of processing cores'20159,003,210'Dynamic voltage transitions'20158,996,899'Independent power control of processing cores'20158,990,597'Instruction for enabling a processor wait state'20158,949,635'Integrated circuit performance improvement across a range of operating conditions and physical constraints'20158,935,546'Dynamic voltage transitions'20158,892,861'Method and apparatus for establishing safe processor operating points'20148,879,346'Mechanisms for enabling power management of embedded dynamic random access memory on a semiconductor integrated circuit package'20148,856,568'Independent power control of processing cores'20148,850,178'Method and apparatus for establishing safe processor operating points'20148,719,600'Dynamic voltage transitions'20148,707,064'Dynamic voltage transitions'20148,611,170'Mechanisms for utilizing efficiency metrics to control embedded dynamic random access memory power states on a semiconductor integrated circuit package'20138,464,035'Instruction for enabling a processor wait state'20138,397,090'Operating integrated circuit logic blocks at independent voltages with single voltage supply'20138,131,989'Method and apparatus for establishing safe processor operating points'20128,069,358'Independent power control of processing cores'20117,949,887'Independent power control of processing cores'20117,890,781'Dynamic voltage transitions'20117,444,524'Dynamic voltage transitions'20087,370,189'Method and apparatus for establishing safe processor operating points in connection with a secure boot'20087,315,952'Power state coordination between devices sharing power-managed resources'20087,290,155'Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit'20077,272,741'Hardware coordination of power management activities'20077,266,712'Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit'20077,237,128'Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device'20077,158,911'Methods and apparatus for thermal management of an integrated circuit die'20077,117,114'On-die temperature control data for communicating to a thermal actuator'20067,013,406'Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device'20066,980,918'Methods and apparatus for thermal management of an integrated circuit die'20056,981,163'Method and apparatus for power mode transition in a multi-thread processor'20056,789,037'Methods and apparatus for thermal management of an integrated circuit die'20046,775,786'Method and apparatus for power mode transition in a multi-thread processor'20046,393,374'Programmable thermal management of an integrated circuit die'20026,308,279'Method and apparatus for power mode transition in a multi-thread processor'20015,860,106'Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem'19995,781,783'Method and apparatus for dynamically adjusting the power consumption of a circuit block within an integrated circuit'19985,745,375'Apparatus and method for controlling power usage'19985,544,092'Method and apparatus for configuring an integrated circuit'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2021Patents assigned to INTEL CORP (80)· patent assignee history
1996–2005Based in Folsom, CA, US· patent location history
1999Based in Vacaville, CA, US· patent location history
2004–2021Based in Beaverton, OR, US· patent location history
2011–2017Patents assigned to GUNTHER STEPHEN H (24)· patent assignee history
2011–2015Patents assigned to GREINER ROBERT (9)· patent assignee history
2011–2015Patents assigned to JOURDAN STEPHAN (7)· patent assignee history
2011–2015Patents assigned to BURTON EDWARD A (6)· patent assignee history
2015Based in Portland, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 80 | 1996–2021 |
| GUNTHER STEPHEN Hself | 24 | 2011–2017 |
| GREINER ROBERT | 9 | 2011–2015 |
| JOURDAN STEPHAN | 7 | 2011–2015 |
| BURTON EDWARD A | 6 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 71 | 2004–2021 |
| Folsom, California, US | 7 | 1996–2005 |
| Portland, OR, US | 1 | 2015 |
| Vacaville, California, US | 1 | 1999 |