Inventor
YU-TENG DAI
Inventor
TW
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H01LSemiconductor devices34%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10DInorganic electric semiconductor devices9%
B82YSpecific uses or applications of nanostructures2%
G11CStatic stores2%
H01FMagnets2%
H10BElectronic memory devices2%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
12,532,500Semiconductor structure202612,424,488Dual etch-stop layer structure202512,406,924Interconnection structure and methods of forming the same202512,362,231Self-assembled dielectric on metal rie lines to increase reliability202512,322,723Self-aligned interconnect structure202512,315,817Dielectric on wire structure to increase processing window for overlying via202512,300,541Structure and formation method of semiconductor device with carbon-containing conductive structure202512,300,611Interconnect conductive structure comprising two conductive materials202512,266,565Integrated chip with an etch-stop layer forming a cavity202512,243,775Double patterning approach by direct metal etch202512,178,051Magnetic random access memory and manufacturing method thereof202412,125,795Integrated chip with inter-wire cavities202412,094,823Interconnection structure and methods of forming the same202411,972,975Semiconductor device structure having air gap and method for forming the same202411,942,364Selective deposition of a protective layer to reduce interconnect structure critical dimensions202411,923,293Barrier structure on interconnect wire to increase processing window for overlying via202411,854,965Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability202311,842,924Dual etch-stop layer structure202311,842,966Integrated chip with inter-wire cavities202311,837,546Self-aligned cavity strucutre202311,805,658Magnetic random access memory and manufacturing method thereof202311,798,910Self-aligned interconnect structure202311,798,840Self-assembled dielectric on metal RIE lines to increase reliability202311,756,884Interconnection structure and methods of forming the same202311,688,782Semiconductor structure and method for forming the same202311,652,054Dielectric on wire structure to increase processing window for overlying via202311,569,127Double patterning approach by direct metal etch202311,521,896Selective deposition of a protective layer to reduce interconnect structure critical dimensions202211,488,926Self-aligned interconnect structure202211,482,447Method of forming an integrated chip having a cavity between metal features202211,362,030Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability202211,302,641Self-aligned cavity strucutre2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (32)· patent assignee history
2022–2026Based in TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 32 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 32 | 2022–2026 |