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Inventor

Keith R. Schakel

Inventor
San Jose, CA, US

Overview

53→
Patents
2002–2018
Patent span
Physics
Primary field (CPC G)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores43%
G06FElectric digital data processing27%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%
H04LTransmission of digital information, e.g. telegraphic communication5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%
H04QSelecting1%
PatentTitleYear
10,013,371Configurable memory circuit system and method20189,727,458'Translating an address associated with a command communicated between a system and memory circuits'20179,632,929'Translating an address associated with a command communicated between a system and memory circuits'20179,542,352'System and method for reducing command scheduling constraints of memory circuits'20179,542,353'System and method for reducing command scheduling constraints of memory circuits'20179,507,739'Configurable memory circuit system and method'20169,171,585'Configurable memory circuit system and method'20159,047,976'Combined signal delay and power saving for use with a plurality of memory circuits'20158,949,519'Simulating a memory circuit'20158,868,829'Memory circuit system and method'20148,797,779'Memory module with memory stack and interface with enhanced capabilites'20148,773,937'Memory refresh apparatus and method'20148,745,321'Simulating a memory standard'20148,671,244'Simulating a memory standard'20148,667,312'Performing power management operations'20148,601,204'Simulating a refresh operation latency'20138,595,419'Memory apparatus operable to perform a power-saving operation'20138,566,556'Memory module with memory stack and interface with enhanced capabilities'20138,566,516'Refresh management of memory modules'20138,359,187'Simulating a different number of memory circuit devices'20138,340,953'Memory circuit simulation with power saving capabilities'20128,280,714'Memory circuit simulation system and method with refresh capabilities'20128,244,971'Memory circuit system and method'20128,209,479'Memory circuit system and method'20128,181,048'Performing power management operations'20128,154,935'Delaying a signal communicated from a system to at least one of a plurality of memory circuits'20128,112,266'Apparatus for simulating an aspect of a memory circuit'20128,089,795'Memory module with memory stack and interface with enhanced capabilities'20128,090,897'System and method for simulating an aspect of a memory circuit'20128,077,535'Memory refresh apparatus and method'20118,041,881'Memory device with emulated characteristics'20118,019,589'Memory apparatus operable to perform a power-saving operation'20117,809,852'High jitter scheduling of interleaved frames in an arbitrated loop'20107,761,724'Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit'20107,730,338'Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits'20107,724,589'System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits'20107,609,567'System and method for simulating an aspect of a memory circuit'20097,590,796'System and method for power management in memory systems'20097,580,312'Power saving system and method for use with a plurality of memory circuits'20097,581,127'Interface circuit system and method for performing power saving operations during a command-related latency'20097,472,220'Interface circuit system and method for performing power management operations utilizing power management signals'20087,406,041'System and method for late-dropping packets in a network switch'20087,392,338'Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits'20087,386,656'Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit'20087,283,556'Method and system for managing time division multiplexing (TDM) timeslots in a network switch'20077,227,841'Packet input thresholding for resource distribution in a network switch'20077,215,680'Method and apparatus for scheduling packet flow on a fibre channel arbitrated loop'20076,687,789'Cache which provides partial tags from non-predicted ways to direct search if way prediction misses'20046,647,490'Training line predictor for branch targets'20036,636,959'Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition'20036,622,237'Store to load forward predictor training using delta tag'20036,546,478'Line predictor entry with location pointers and control information for corresponding instructions in a cache line'20036,502,185'Pipeline elements which verify predecode information'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2018Based in San Jose, CA, US· patent location history
2010–2017Patents assigned to GOOGLE INC (34)· patent assignee history
2011–2017Patents assigned to SCHAKEL KEITH R (27)· patent assignee history
2011–2017Patents assigned to WANG DAVID T (27)· patent assignee history
2011–2017Patents assigned to RAJAN SURESH NATARAJAN (26)· patent assignee history
2011–2017Patents assigned to WEBER FREDERICK DANIEL (26)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
GOOGLE INC342010–2017
SCHAKEL KEITH Rself272011–2017
WANG DAVID T272011–2017
RAJAN SURESH NATARAJAN262011–2017
WEBER FREDERICK DANIEL262011–2017
Locations
LocationPatentsSpan
San Jose, California, US532002–2018