Inventor

Mauricio J. Serrano

Inventor

Bronx, NY, US

Overview

2001–2021

Patent span

Physics

Primary field (CPC G)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing87%

G06EOptical computing devices4%

G06NComputing arrangements based on specific computational models4%

H04LTransmission of digital information, e.g. telegraphic communication4%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

11,132,228SMT processor to create a virtual vector register file for a borrower thread from a number of donated vector register files2021 10,984,073Dual phase matrix-vector multiplication system2021 10,884,942Reducing memory access latency in scatter/gather operations2021 10,795,683Predicting indirect branches using problem branch filtering and pattern cache2020 10,713,056Wide vector execution in single thread mode for an out-of-order processor2020 10,705,847Wide vector execution in single thread mode for an out-of-order processor2020 10,664,279Instruction prefetching in a computer processor using a prefetch prediction vector2020 10,558,429Switching matrix representation for an incremental algorithm computing connected components2020 10,417,304Dual phase matrix-vector multiplication system2019 10,379,857Dynamic sequential instruction prefetching2019 10,175,987Instruction prefetching in a computer processor using a prefetch prediction vector2019 10,078,514Techniques for dynamic sequential instruction prefetching2018 9,983,878Branch prediction using multiple versions of history data2018 9,928,158'Redundant transactions for detection of timing sensitive errors'2018 9,904,551'Branch prediction using multiple versions of history data'2018 9,898,295'Branch prediction using multiple versions of history data'2018 9,778,967'Sophisticated run-time system for graph processing'2017 9,772,890'Sophisticated run-time system for graph processing'2017 9,619,356'Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor'2017 9,524,166'Tracking long GHV in high performance out-of-order superscalar processors'2016 9,495,164'Branch prediction using multiple versions of history data'2016 9,483,271'Compressed indirect prediction caches'2016 9,459,979'Detection of hardware errors using redundant transactions for system test'2016 9,400,700'Optimized system for analytics (graphs and sparse matrices) operations'2016 9,304,863'Transactions for checkpointing and reverse execution'2016 9,304,835'Optimized system for analytics (graphs and sparse matrices) operations'2016 9,251,014'Redundant transactions for detection of timing sensitive errors'2016 9,189,365'Hardware-assisted program trace collection with selectable call-signature capture'2015 8,756,582'Tracking a programs calling context using a hybrid code signature'2014 8,756,581'Adaptive next-executing-cycle trace selection for trace-driven code optimizers'2014 8,621,150'Data placement optimization using data context collected during garbage collection'2013 8,489,866'Branch trace history compression'2013 8,479,184'General purpose emit for use in value profiling'2013 8,122,438'Computer implemented method and system for accurate, efficient and adaptive calling context profiling'2012 7,921,260'Preferred write-mostly data cache replacement policies'2011 7,900,026'Target branch prediction using a plurality of tables'2011 7,818,722'Computer implemented method and system for accurate, efficient and adaptive calling context profiling'2010 7,793,049'Mechanism for data cache replacement based on region policies'2010 7,577,947'Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects'2009 7,490,117'Dynamic performance monitoring-based approach to memory management'2009 7,434,037'System for target branch prediction using correlation of local target histories including update inhibition for inefficient entries'2008 7,389,385'Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis'2008 6,973,646'Method for compiling program components in a mixed static and dynamic environment'2005 6,530,079'Method for optimizing locks in computer programs'2003 6,381,738'Method for optimizing creation and destruction of objects in computer programs'2002 6,292,938'Retargeting optimized code by matching tree patterns in directed acyclic graphs'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Patents assigned to IBM (43)· patent assignee history

2001–2009Based in San Jose, CA, US· patent location history

2008–2009Patents assigned to INTEL CORP (3)· patent assignee history

2008–2021Based in Bronx, NY, US· patent location history

2012–2013Patents assigned to SERRANO MAURICIO JOSE (3)· patent assignee history

2012–2013Patents assigned to ZHUANG XIAOTONG (2)· patent assignee history

2013–2014Patents assigned to SERRANO MAURICIO J (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	43	2001–2021
INTEL CORP	3	2008–2009
SERRANO MAURICIO Jself	3	2013–2014
SERRANO MAURICIO JOSEself	3	2012–2013
ZHUANG XIAOTONG	2	2012–2013

Locations

Location	Patents	Span
Bronx, New York, US	39	2008–2021
San Jose, California, US	7	2001–2009