Inventor

Ron Gabor

Inventor
Hertzliya, IL

Overview

53→
Patents
2008–2021
Patent span
Physics
Primary field (CPC G)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing73%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use19%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%
G11CStatic stores3%
PatentTitleYear
11,068,339Read from memory instructions, processors, methods, and systems, that do not take exception on defective data202111,030,030Enhanced address space layout randomization202110,976,961Device, system and method to detect an uninitialized memory read202110,891,230Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits202110,877,897System, apparatus and method for multi-cacheline small object memory tagging202010,802,567Performing local power gating in a processor202010,776,190Hardware apparatuses and methods for memory corruption detection202010,725,849Server RAS leveraging multi-key encryption202010,725,788Advanced error detection for integer single instruction, multiple data (SIMD) arithmetic operations202010,725,755Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads202010,649,783Multicore system for fusing instructions queued during a dynamically adjustable time window202010,585,741Heap management for memory corruption detection202010,521,361Memory write protection for memory corruption detection architectures201910,346,171End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structures201910,324,857Linear memory address transformation and management201910,319,458Hardware apparatuses and methods to check data storage devices for transient faults201910,296,416Read from memory instructions, processors, methods, and systems, that do not take exception on defective data201910,191,791Enhanced address space layout randomization201910,162,694Hardware apparatuses and methods for memory corruption detection201810,156,884Local power gate (LPG) interfaces for power-aware operations201810,133,620Detecting errors in register renaming by comparing value representing complete error free set of identifiers and value representing identifiers in register rename unit201810,095,573Byte level granularity buffer overflow detection for memory corruption detection architectures201810,073,727Heap management for memory corruption detection20189,934,164Memory write protection for memory corruption detection architectures20189,904,586'Interfacing with block-based storage in a processor'20189,858,140'Memory corruption detection'20189,772,674'Performing local power gating in a processor'20179,766,968'Byte level granularity buffer overflow detection for memory corruption detection architectures'20179,690,591'System and method for fusing instructions queued during a time window defined by a delay counter'20179,690,640'Recovery from multiple data errors'20179,672,019'Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads'20179,652,375'Multiple chunk support for memory corruption detection architectures'20179,619,313'Memory write protection for memory corruption detection architectures'20179,595,349'Hardware apparatuses and methods to check data storage devices for transient faults'20179,519,324'Local power gate (LPG) interfaces for power-aware operations'20169,292,362'Method and apparatus to protect a processor against excessive power usage'20169,229,524'Performing local power gating in a processor'20169,003,421'Acceleration threads on idle OS-visible thread execution units'20158,935,514'Optimizing performance of instructions based on sequence detection or information associated with the instructions'20158,909,988'Recoverable parity and residue error'20148,782,374'Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor'20148,706,979'Code reuse and locality hinting'20148,543,796'Optimizing performance of instructions based on sequence detection or information associated with the instructions'20138,433,850'Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor'20138,347,035'Posting weakly ordered transactions'20138,166,320'Power aware software pipelining for hardware accelerators'20128,127,085'Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor'20128,103,831'Efficient method and apparatus for employing a micro-op cache in a processor'20127,900,031'Multiple, cooperating operating systems (OS) platform system and method'20117,827,551'Real-time threading service for partitioned multiprocessor systems'20107,725,745'Power aware software pipelining for hardware accelerators'20107,650,273'Performance simulation of multiprocessor systems'20107,437,546'Multiple, cooperating operating systems (OS) platform system and method'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2021Patents assigned to INTEL CORP (53)· patent assignee history
2008–2017Based in Raanana, IL· patent location history
2012–2017Patents assigned to GABOR RON (14)· patent assignee history
2012–2017Patents assigned to RAPPOPORT LIHU (6)· patent assignee history
2012–2017Patents assigned to OUZIEL IDO (4)· patent assignee history
2012–2014Patents assigned to SALA FRANCK (4)· patent assignee history
2014–2021Based in Herzliya, IL· patent location history
2015–2017Based in Ra'anana, IL· patent location history
2016–2021Based in Hertzliya, IL· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP532008–2021
GABOR RONself142012–2017
RAPPOPORT LIHU62012–2017
OUZIEL IDO42012–2017
SALA FRANCK42012–2014
Locations
LocationPatentsSpan
Hertzliya, IL272016–2021
Raanana, IL152008–2017
Herzliya, IL72014–2021
Ra'anana, IL42015–2017