Inventor

Gary Chen

Inventor
Boise, ID, US

Overview

48→
Patents
2000–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 48 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H10DInorganic electric semiconductor devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
C06BExplosives or thermic compositions4%
C06CDetonating or priming devices4%
H01LSemiconductor devices3%
H10BElectronic memory devices3%
F28FDetails of heat-exchange and heat-transfer apparatus, of general application2%
F42BExplosive charges, e.g. for blasting, fireworks, ammunition2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
PatentTitleYear
D0914652Wireless earphone2021D0909094Recliner cover202110,774,846Portable, low-power air filtration system202010,666,149Control circuit for switching power supply202010,630,359Method and apparatus for beamforming training using frames202010,330,617Wearable sensor badge for toxic industrial chemicals20199,702,678'Armor piercing incendiary projectile'20179,669,932'Display mounting system for reduced HIC'20179,490,695'Method and apparatus for eliminating shimmering'20169,252,265'Shielded gate trench MOS with improved source pickup layout'20168,994,101'Shielded gate trench MOS with improved source pickup layout'20158,889,510'Surrounding stacked gate multi-gate FET structure nonvolatile memory device'20148,614,487'Split dual gate field effect transistor'20138,608,879'Environmentally friendly flare illuminant composition'20138,513,727'Surrounding stacked gate multi-gate FET structure nonvolatile memory device'20138,471,323'3-D electrically programmable and erasable single-transistor non-volatile semiconductor memory device'20138,431,457'Method for fabricating a shielded gate trench MOS with improved source pickup layout'20138,093,114'Method for making split dual gate field effect transistor'20127,582,517'Method for making split dual gate field effect transistor'20097,578,895'Perchlorate free flash bang compositions for pyrotechnic training rounds'20097,478,594'Laser primer'20097,459,043'Moisture-resistant black powder substitute compositions'20087,460,367'Method and system for dissipating thermal energy from conduction-cooled circuit card assemblies which employ remote heat sinks and heat pipe technology'20087,437,995'Axially compact mechanical igniter for thermal batteries and the like'20087,211,200'Manufacture and cleaning of a semiconductor'20077,108,055'Optimized heat sink using high thermal conducting base and low thermal conducting fins'20067,087,534'Semiconductor substrate cleaning'20066,933,580'Semiconductor structure with substantially etched oxynitride defects protruding therefrom'20056,890,865'Low k film application for interlevel dielectric and method of cleaning etched features'20056,815,368'Semiconductor substrate cleaning'20046,794,307'Method for cleaning residual debris from semiconductor surfaces'20046,758,263'Heat dissipating component using high conducting inserts'20046,743,720'Method of manufacturing a portion of a memory by selectively etching to remove metal nitride or metal oxynitride extrusions'20046,703,303'Method of manufacturing a portion of a memory'20046,693,354'Semiconductor structure with substantially etched nitride defects protruding therefrom'20046,686,275'Method of selectively removing metal nitride or metal oxynitride extrusions from a semmiconductor structure'20046,664,611'Composition and method for cleaning residual debris from semiconductor surfaces'20036,627,913'Insulation of an MRAM device through a self-aligned spacer'20036,605,863'Low k film application for interlevel dielectric and method of cleaning etched features'20036,592,777'Manufacture and cleaning of a semiconductor'20036,573,175'Dry low k film application for interlevel dielectric and method of cleaning etched features'20036,509,278'Method of forming a semiconductor contact that includes selectively removing a Ti-containing layer from the surface'20036,455,906'Gate stack structure with conductive silicide segment that has substantially etched nitride and/or oxynitride defects protruding from its sidewalls'20026,391,794'Composition and method for cleaning residual debris from semiconductor surfaces'20026,358,788'Method of fabricating a wordline in a memory array of a semiconductor device'20026,224,424'Multi-line signal cable'20016,174,391'Magnesium-fueled pyrotechnic compositions and processes based on elvax-cyclohexane coating technology'20016,162,738'Cleaning compositions for high dielectric structures and methods of using same'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2007Patents assigned to MICRON TECHNOLOGY INC (20)· patent assignee history
2000–2014Based in Boise, ID, US· patent location history
2001–2017Patents assigned to US ARMY (5)· patent assignee history
2001–2017Based in Succasunna, NJ, US· patent location history
2004–2006Based in Parma, OH, US· patent location history
2009–2014Patents assigned to SEMICONDUCTOR MFG INT SHANGHAI (6)· patent assignee history
2009–2016Based in Shanghai, CN· patent location history
2012–2013Patents assigned to CHEN GARY (6)· patent assignee history
2012–2013Patents assigned to LEE ROGER (4)· patent assignee history
2019–2020Based in Chino Hills, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC202000–2007
CHEN GARYself62012–2013
SEMICONDUCTOR MFG INT SHANGHAI62009–2014
US ARMY52001–2017
LEE ROGER42012–2013
Locations
LocationPatentsSpan
Boise, ID, US222000–2014
Succasunna, New Jersey, US72001–2017
Shanghai, CN72009–2016
Chino Hills, California, US22019–2020
Parma, OH, US22004–2006