Inventor
Charles G. Sodini
Inventor
Belmont, MA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
A61Bprimary
A61BDiagnosis14%
G11CStatic stores14%
H04NPictorial communication, e.g. television14%
H03FAmplifiers6%
H03KPulse technique6%
H04LTransmission of digital information, e.g. telegraphic communication6%
H10BElectronic memory devices6%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation6%
B06BMethods or apparatus for generating or transmitting mechanical vibrations of infrasonic, sonic, or ultrasonic frequency, e.g. for performing mechanical work in general3%
G01SRadio direction-finding3%
PatentTitleYear
11,089,966Devices and methods for non-invasive capillary blood pressure measurement202110,806,431Application specific integrated circuit with column-row-parallel architecture for ultrasonic imaging202010,028,661Buffered body return receiver20189,749,164'Asynchronous digital communication'20179,537,473'Digitally assisted analog dynamic range enhancer'20179,078,577'Circuit for heartbeat detection and beat timing extraction'20157,349,574'System and method for processing non-linear image data from a digital imager'20087,319,425'Comparator-based switched capacitor circuit for scaled semiconductor fabrication processes'20086,977,685'Single-chip imager system with programmable dynamic range'20056,928,535'Data input/output configuration for transfer among processing elements of different processors'20056,600,471'Precise MOS imager transfer function control for expanded dynamic range imaging'20036,452,149'Image input system including solid image sensing section and signal processing section'20026,008,703'Digital compensation for wideband modulation of a phase locked loop frequency synthesizer'19995,818,788'Circuit technique for logic integrated DRAM with SIMD architecture and a method for controlling low-power, high-speed and highly reliable operation'19985,491,803'Response resolver for associative memories and parallel processors'19964,831,585'Four transistor cross-coupled bitline content addressable memory'19894,799,192'Three-transistor content addressable memory'19894,198,694'X-Y Addressable memory'19804,163,243'One-transistor memory cell with enhanced capacitance'1979Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1979–1980Patents assigned to HEWLETT PACKARD CO (2)· patent assignee history
1979–1980Based in San Francisco, CA, US· patent location history
1989–2021Patents assigned to MASSACHUSETTS INST TECHNOLOGY (15)· patent assignee history
1989–1998Based in Cambridge, MA, US· patent location history
1996–2020Based in Belmont, MA, US· patent location history
1998Patents assigned to NEC CORP (1)· patent assignee history
2002–2005Patents assigned to TOSHIBA KK (2)· patent assignee history
2017Patents assigned to ANALOG DEVICES INC (1)· patent assignee history
2021Based in Belmont, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MASSACHUSETTS INST TECHNOLOGY | 15 | 1989–2021 |
| HEWLETT PACKARD CO | 2 | 1979–1980 |
| TOSHIBA KK | 2 | 2002–2005 |
| ANALOG DEVICES INC | 1 | 2017 |
| NEC CORP | 1 | 1998 |
Locations
| Location | Patents | Span |
|---|---|---|
| Belmont, Massachusetts, US | 13 | 1996–2020 |
| Cambridge, Massachusetts, US | 3 | 1989–1998 |
| San Francisco, California, US | 2 | 1979–1980 |
| Belmont, California, US | 1 | 2021 |