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Inventor

Osamu Nishii

Inventor
Inagi, JP

Overview

46→
Patents
1993–2019
Patent span
Physics
Primary field (CPC G)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing53%
G11CStatic stores20%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
H04NPictorial communication, e.g. television11%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
PatentTitleYear
10,365,979Lockstepped CPU selection based on failure status20199,734,023'Semiconductor device with output data selection of lockstepped computing elements based on diagnostic information'20178,364,988'Substrate bias switching unit for a low power processor'20138,234,441'Processor system using synchronous dynamic memory'20128,145,889'Data processing system with branch target addressing using upper and lower bit permutation'20127,958,379'Substrate bias switching unit for a low power processor'20117,904,641'Processor system using synchronous dynamic memory'20117,836,286'Data processing system to calculate indexes into a branch target address table based on a current operating mode'2010RE041589'Memory system performing fast access to a memory location by omitting the transfer of a redundant address'20107,475,261'Substrate bias switching unit for a low power processor'20097,376,783'Processor system using synchronous dynamic memory'20087,254,082'Semiconductor device'20077,178,046'Halting clock signals to input and result latches in processing path upon fetching of instruction not supported'20077,143,230'Processor system using synchronous dynamic memory'20067,023,757'Semiconductor device'20067,003,651'Program counter (PC) relative addressing mode with fast displacement'20066,879,188'Semiconductor integrated circuit device'20056,877,087'Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving'20056,715,090'Processor for controlling substrate biases in accordance to the operation modes of the processor'20046,697,908'Processor system using synchronous dynamic memory'20046,654,305'System LSI having a substrate-bias generation circuit with a substrate-bias control-value storage unit'20036,604,202'Low power processor'20036,532,528'Data processor and data processor system having multiple modes of address indexing and operation'20036,515,519'Semiconductor integrated circuit device'20036,493,255'Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device'20026,424,560'Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device'20026,334,166'Processor system using synchronous dynamic memory'20016,292,867'Data processing system'20016,260,107'Processor system using synchronous dynamic memory'20016,154,807'Memory system performing fast access to a memory location by omitting the transfer of a redundant address'20006,092,172'Data processor and data processing system having two translation lookaside buffers'20006,078,983'Multiprocessor system having distinct data bus and address bus arbiters'20006,078,986'Processor system using synchronous dynamic memory'20006,012,139'Microprocessor including floating point unit with 16-bit fixed length instruction set'20005,918,045'Data processor and data processing system'19995,873,122'Memory system performing fast access to a memory location by omitting transfer of a redundant address'19995,740,401'Multiprocessor system having a processor invalidating operand cache when lock-accessing'19985,652,858'Method for prefetching pointer-type data structure and information processing apparatus therefor'19975,574,876'Processor system using synchronous dynamic memory'19965,557,760'Integrated circuit data processor including a control pin for deactivating the driving of a data bus without deactivating that of an address bus'19965,375,215'Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank'19945,301,285'Data processor having two instruction registers connected in cascade and two instruction decoders'19945,287,484'Multi-processor system for invalidating hierarchical cache'19945,283,886'Multiprocessor cache system having three states for generating invalidating signals upon write accesses'19945,267,198'Static memory containing sense amp and sense amp switching circuit'19935,193,075'Static memory containing sense AMP and sense AMP switching circuit'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2007Patents assigned to HITACHI LTD (27)· patent assignee history
1993–1994Patents assigned to HITACHI VLSI ENG (3)· patent assignee history
1993–2013Based in Tokyo, JP· patent location history
1994–2012Based in Kokubunji, JP· patent location history
1997–2010Based in Inagi, JP· patent location history
2004–2011Patents assigned to RENESAS TECH CORP (11)· patent assignee history
2010–2019Patents assigned to RENESAS ELECTRONICS CORP (7)· patent assignee history
2012–2013Patents assigned to NISHII OSAMU (3)· patent assignee history
2017–2019Based in Kanagawa, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
HITACHI LTD271993–2007
RENESAS TECH CORP112004–2011
RENESAS ELECTRONICS CORP72010–2019
HITACHI VLSI ENG31993–1994
NISHII OSAMUself32012–2013
Locations
LocationPatentsSpan
Inagi, JP211997–2010
Kokubunji, JP161994–2012
Tokyo, JP71993–2013
Kanagawa, JP22017–2019