Inventor

Harry-Hak-Lay Chuang

Inventor
Singapore, SG

Overview

339→
Patents
2003–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 339 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices31%
H01LSemiconductor devices25%
H10BElectronic memory devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10NElectric solid-state devices not otherwise provided for5%
G11CStatic stores3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
G06FElectric digital data processing1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices0%
PatentTitleYear
11,121,308Sidewall spacer structure for memory cell202111,101,371Structure and method for vertical tunneling field effect transistor with leveled source and drain202111,094,545Self-aligned insulated film for high-K metal gate device202111,088,199Semiconductor device202111,088,083DC and AC magnetic field protection for MRAM device using magnetic-field-shielding structure202111,075,335Techniques for MRAM MTJ top electrode connection202111,063,058Memory device with metal gate202111,063,208Embedded MRAM fabrication process for ion beam etching with protection by top electrode spacer202111,056,566Split gate memory device and method of fabricating the same202110,878,928One-time-programmable (OTP) implementation using magnetic junctions202010,877,089Semiconductor wafer testing system and related method for improving external magnetic field wafer testing202010,868,024Method of forming embedded nonvolatile memory202010,868,234Storage device having magnetic tunnel junction cells of different sizes, and method of forming storage device202010,861,954High-K film apparatus and method202010,840,149Fabrication method of a metal gate structure202010,825,498Magnetic random access memory structure and manufacturing method of the same202010,825,499Magnetic random access memory structure and manufacturing method of the same202010,818,609Package structure and method for fabricating the same202010,811,504Semiconductor structure for flash memory cells and method of making same202010,797,230Techniques for MRAM MTJ top electrode to metal layer interface including spacer202010,790,439Memory cell with top electrode via202010,748,895Semiconductor arrangement and formation thereof202010,727,272Semiconductor structure and manufacturing method of the same202010,727,274Techniques for MRAM top electrode via connection202010,720,571Magnetic memory structure and method of forming the same202010,692,750Method for fabricating a semiconductor device202010,686,125Memory device202010,672,760Semiconductor die202010,672,975Magnetic tunnel junction with reduced damage202010,665,600Memory devices and method of fabricating same202010,658,373Method for manufacturing semiconductor device with metal gate memory device and metal gate logic device202010,658,492Polysilicon design for replacement gate technology202010,636,961Semiconductor structure and method of forming the same202010,553,699Gate structure of a semiconductor device202010,553,580Method of manufacturing semiconductor device202010,535,675High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory202010,535,814Techniques for MRAM MTJ top electrode connection202010,522,740Techniques for MRAM MTJ top electrode to metal layer interface including spacer201910,516,026Split gate memory device and method of fabricating the same201910,510,803Semiconductor memory device and method for fabricating the same201910,510,763Embedded nonvolatile memory and forming method thereof201910,510,802Semiconductor device and method of manufacturing the same201910,510,804Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof201910,504,958Semiconductor structure and manufacturing method of the same201910,497,861Manufacturing techniques and corresponding devices for magnetic tunnel junction devices201910,490,654Vertical tunneling field-effect transistor cell and fabricating the same201910,490,460Semiconductor arrangement and method of forming201910,490,248Magnetic random access memory structure and manufacturing method of the same201910,453,932Semiconductor structure for flash memory cells and method of making same201910,424,652Vertical tunneling field-effect transistor cell and fabricating the same201910,418,361Circuit incorporating multiple gate stack compositions201910,403,736Polysilicon design for replacement gate technology201910,388,531Self-aligned insulated film for high-k metal gate device201910,332,882Semiconductor device having protective structure over shallow trench isolation region and fabricating method thereof201910,304,903Semiconductor structure201910,276,447Semiconductor structures and methods of forming the same201910,276,588HKMG high voltage CMOS for embedded non-volatile memory201910,270,026Multilayered spacer structure for a magnetic tunneling junction and method of manufacturing201910,270,025Semiconductor structure having magnetic tunneling junction (MTJ) layer201910,177,238High-K film apparatus and method201910,163,919Embedded flash memory device with floating gate embedded in a substrate201810,164,169Memory device having a single bottom electrode layer201810,164,076Vertical tunneling field-effect transistor cell and fabricating the same201810,147,794Split gate memory device and method of fabricating the same201810,134,743Structure and method for statice random access memory device of vertical tunneling field effect transistor201810,134,807Structure and formation method of integrated circuit structure201810,109,790Method for manufacturing mixed-dimension and void-free MRAM structure201810,103,253Structure and method for vertical tunneling field effect transistor with leveled source and drain201810,084,061Polysilicon design for replacement gate technology201810,068,836Metal gate transistor, integrated circuits, systems, and fabrication methods thereof201810,068,945Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof201810,068,773Contact formation for split gate flash memory201810,050,047Method to improve floating gate uniformity for non-volatile memory device201810,050,050Semiconductor device with metal gate memory device and metal gate logic device and method for manufacturing the same201810,043,970Determining a characteristic of a monitored layer on an integrated chip201810,038,137MRAM device and method for fabricating the same201810,032,828Semiconductor memory device and method for fabricating the same201810,026,656Metal gate features of semiconductor die201810,008,538Semiconductor structure and method of forming the same20189,985,075Dummy bottom electrode in interconnect to reduce CMP dishing20189,978,759Memory devices and method of forming same20189,978,850Contact for high-k metal gate device20189,978,853Method of forming gate structure of a semiconductor device20189,972,524Method for fabricating a semiconductor device20189,929,168'Embedded memory and methods of forming the same'20189,929,251'Polysilicon design for replacement gate technology'20189,911,805'Silicon recess etch and epitaxial deposit for shallow trench isolation (STI)'20189,905,751'Magnetic tunnel junction with reduced damage'20189,893,278'Embedded memory device between noncontigous interconnect metal layers'20189,893,120'Semiconductor structure and method of forming the same'20189,865,716'System and method for a vertical tunneling field-effect transistor cell'20189,865,510'Device and methods for high-K and metal gate slacks'20189,865,610'Si recess method in HKMG replacement gate technology'20189,853,125Vertical tunneling field-effect transistor cell and fabricating the same20179,842,986'Semiconductor structure and method of forming the same'20179,837,322Semiconductor arrangement and method of forming20179,831,235Method of making structure having a gate stack20179,818,935'Techniques for MRAM MTJ top electrode connection'20179,806,172'Vertical tunneling field-effect transistor cell and fabricating the same'20179,780,180'Semiconductor device with partially unsilicided source/drain'20179,780,301'Method for manufacturing mixed-dimension and void-free MRAM structure'20179,779,947'Self-aligned insulated film for high-k metal gate device'20179,768,076'Semiconductor device and method of forming the same'20179,767,878'Semiconductor memory device and method for controlling the same'20179,741,728'Method for forming a split-gate flash memory cell device with a low power logic device'20179,735,245'Recessed salicide structure to integrate a flash memory device with a high κ, metal gate logic device'20179,721,947'Semiconductor device and method of manufacturing'20179,716,222'Semiconductor structure and method for manufacturing the same'20179,711,605'Contact for high-k metal gate device'20179,691,876'Enhanced gate replacement process for high-K metal gate technology'20179,691,969'Semiconductor integrated circuit and method of making the same'20179,685,395'Wiring layout having differently shaped vias'20179,679,979'Semiconductor structure for flash memory cells and method of making same'20179,679,817'Semiconductor structures and methods of forming the same'20179,679,988'Polysilicon design for replacement gate technology'20179,679,909'Method for manufacturing a finger trench capacitor with a split-gate flash memory cell'20179,673,205'Embedded nonvolatile memory and forming method thereof'20179,673,194'Semiconductor arrangement and formation thereof'20179,666,790'Manufacturing techniques and corresponding devices for magnetic tunnel junction devices'20179,659,953'HKMG high voltage CMOS for embedded non-volatile memory'20179,634,243'Semiconductor structure and method of forming the same'20179,627,392'Method to improve floating gate uniformity for non-volatile memory devices'20179,620,620'Methods to stop contact metal from extruding into replacement gates'20179,620,421'Metal gate transistor, integrated circuits, systems, and fabrication methods thereof'20179,620,372'HK embodied flash memory and methods of forming the same'20179,607,121'Cascode CMOS structure'20179,595,443'Metal gate structure of a semiconductor device'20179,590,059'Interdigitated capacitor to integrate with flash memory'20179,583,591'Si recess method in HKMG replacement gate technology'20179,576,855'Device and methods for high-k and metal gate stacks'20179,577,051'Spacer structures of a semiconductor device'20179,570,539'Integration techniques for MIM or MIP capacitors with flash memory and/or high-κ metal gate CMOS technology'20179,559,177'Memory devices and method of fabricating same'20179,543,153'Recess technique to embed flash memory in SOI technology'20179,536,888'Method to prevent oxide damage and residue contamination for memory device'20179,536,977'Vertical tunneling field-effect transistor cell and fabricating the same'20179,525,040'Method of fabricating hybrid impact-ionization semiconductor device'20169,515,069'Semiconductor die'20169,508,721'Metal gate structure of a CMOS semiconductor device'20169,502,514'Memory devices and method of forming same'20169,502,533'Silicon recess etch and epitaxial deposit for shallow trench isolation (STI)'20169,502,466'Dummy bottom electrode in interconnect to reduce CMP dishing'20169,496,276'CMP fabrication solution for split gate memory embedded in HK-MG process'20169,484,352'Method for forming a split-gate flash memory cell device with a low power logic device'20169,484,351'Split gate memory device and method of fabricating the same'20169,478,633'Method and apparatus of forming ESD protection device'20169,472,636'Cost-effective gate replacement process'20169,466,714'Vertical tunneling field-effect transistor cell with coaxially arranged gate contacts and drain contacts'20169,455,344'Integrated circuit metal gate structure having tapered profile'20169,431,500'Integrated circuit device having defined gate spacing and method of designing and fabricating thereof'20169,431,413'STI recess method to embed NVM memory in HKMG replacement gate technology'20169,425,206'Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology'20169,419,099'Method of fabricating spacers in a strained semiconductor device'20169,412,841'Method of fabricating a transistor using contact etch stop layers'20169,406,669'Method and structure for vertical tunneling field effect transistor and planar devices'20169,397,112'L-shaped capacitor in thin film storage technology'20169,390,927'Contact formation for split gate flash memory'20169,378,961'Methods of fabricating multiple gate stack compositions'20169,368,603'Contact for high-k metal gate device'20169,355,209'Revising layout design through OPC to reduce corner rounding effect'20169,349,742'Embedded memory and methods of forming the same'20169,349,655'Method for mechanical stress enhancement in semiconductor devices'20169,337,194'Semiconductor device and method of forming the same'20169,324,622'Semiconductor device and method of forming the same'20169,299,696'Semiconductor structure with suppressed STI dishing effect at resistor region'20169,287,279'Silicon nitride (SiN) encapsulating layer for silicon nanocrystal memory storage'20169,276,010'Dual silicide formation method to embed split gate flash memory in high-k metal gate (HKMG) technology'20169,263,396'Photo alignment mark for a gate last process'20169,252,224'Self-aligned insulated film for high-k metal gate device'20169,230,977'Embedded flash memory device with floating gate embedded in a substrate'20169,231,084'Method of forming laterally diffused metal oxide semiconductor transistor with partially unsilicided source/drain'20169,219,124'Metal gate semiconductor device'20159,219,125'Device and methods for high-k and metal gate stacks'20159,209,090'Method of forming a semiconductor die'20159,202,817'Semiconductor device and method for manufacturing the same'20159,196,611'Reduced substrate coupling for inductors in semiconductor devices'20159,190,326'Semiconductor device having a post feature and method of manufacturing the same'20159,190,484'Vertical tunneling field-effect transistor cell and fabricating the same'20159,184,252'Flash memory embedded with HKMG technology'20159,159,842'Embedded nonvolatile memory'20159,159,826'Vertical tunneling field-effect transistor cell and fabricating the same'20159,153,581'Vertical tunneling field-effect transistor cell and fabricating the same'20159,147,736'High-K film apparatus and method'20159,142,414'CMOS devices with metal gates and methods for forming the same'20159,136,393'HK embodied flash memory and methods of forming the same'20159,129,823'Silicon recess ETCH and epitaxial deposit for shallow trench isolation (STI)'20159,123,745'Device with a vertical gate structure'20159,117,894'Contact etch stop layers of a field effect transistor'20159,117,840'Method of fabricating spacers in a strained semiconductor device'20159,111,780'Structure and method for vertical tunneling field effect transistor with leveled source and drain'20159,105,692'Method of fabricating an interconnection structure in a CMOS comprising a step of forming a dummy electrode'20159,099,467'E-fuse structure design in electrical programmable redundancy for embedded memory circuit'20159,082,651'Memory devices and method of forming same'20159,082,630'Semiconductor device and fabricating method thereof'20159,076,672'Cost-effective gate replacement process'20159,070,623'Controlling gate formation for high density cell layout'20159,070,784'Metal gate structure of a CMOS semiconductor device and method of forming the same'20159,059,310'SRAM devices utilizing strained-channel transistors and methods of manufacture'20159,059,022'Semiconductor structures and methods of forming the same'20159,054,025'Process for controlling shallow trench isolation step height'20159,048,335'Method of fabricating multiple gate stack compositions'20159,029,940'Vertical tunneling field-effect transistor cell'20159,006,860'Metal gate features of semiconductor die'20159,000,533'Device and methods for high-K and metal gate stacks'20158,981,495'Laterally diffused metal oxide semiconductor transistor with partially unsilicided source/drain'20158,981,562'Wiring layout having differently shaped vias'20158,981,530'Semiconductor device and method of forming the same'20158,969,949'Structure and method for static random access memory device of vertical tunneling field effect transistor'20158,970,015'Method for protecting a gate structure during contact formation'20158,969,972'Modifying work function in PMOS devices by counter-doping'20158,940,596'Method of making structure having a gate stack'20158,932,951'Dishing-free gap-filling with multiple CMPs'20158,890,260'Polysilicon design for replacement gate technology'20148,889,501'Methods for forming MOS devices with raised source/drain regions'20148,883,594'Vertical tunneling field-effect transistor cell and fabricating the same'20148,871,625'Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers'20148,853,753'Contact for high-k metal gate device'20148,846,510'Method and structure to boost MOSFET performance and NBTI'20148,847,321'Cascode CMOS structure'20148,836,035'Method and apparatus for reducing gate resistance'20148,835,294'Method for improving thermal stability of metal gate'20148,828,838'Large dimension device and method of manufacturing same in gate last process'20148,803,202'Layout methods of integrated circuits having unit MOS devices'2014RE045060'Spacer structures of a semiconductor device'20148,772,147'Spacer structures of a semiconductor device'20148,765,600'Contact structure for reducing gate resistance and method of making the same'20148,754,470'Vertical tunneling field-effect transistor cell and fabricating the same'20148,735,235'Integrated circuit metal gate structure and method of fabrication'20148,728,900'Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors'20148,716,103'Semiconductor device and method of fabricating same'20148,697,517'Reduced substrate coupling for inductors in semiconductor devices'20148,680,597'Method and apparatus for improving gate contact'20148,680,619'Method of fabricating hybrid impact-ionization semiconductor device'20148,669,153'Integrating a first contact structure in a gate last process'20148,664,079'Method of fabricating semiconductor device by thinning hardmask layers on frontside and backside of substrate'20148,648,446'Method for protecting a gate structure during contact formation'20148,629,515'Metal gate semiconductor device'20148,629,050'E-fuse structure design in electrical programmable redundancy for embedded memory circuit'20148,624,295'SRAM devices utilizing strained-channel transistors and methods of manufacture'20148,614,484'High voltage device with partial silicon germanium epi source/drain'20138,609,484'Method for forming high-K metal gate device'20138,598,656'Method and apparatus of forming ESD protection device'20138,598,630'Photo alignment mark for a gate last process'20138,587,074'Device having a gate stack'20138,586,428'Interconnection structure for N/P metal gates'20138,563,389'Integrated circuit having silicon resistor and method of forming the same'20138,557,659'Spacer structures of a semiconductor device'20138,558,278'Strained transistor with optimized drive current and method of forming'20138,552,522'Dishing-free gap-filling with multiple CMPs'20138,524,570'Method and apparatus for improving gate contact'20138,525,270'Structures and methods to stop contact metal from extruding into replacement gates'20138,497,169'Method for protecting a gate structure during contact formation'20138,476,126'Gate stack for high-K/metal gate last process'20138,461,654'Spacer shape engineering for void-free gap-filling process'20138,461,621'Method and apparatus of forming bipolar transistor device'20138,461,629'Semiconductor device and method of fabricating same'20138,450,834'Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers'20138,450,216'Contact etch stop layers of a field effect transistor'20138,450,161'Method of fabricating a sealing structure for high-k metal gate'20138,394,692'Integrating a first contact structure in a gate last process'20138,390,072'Chemical mechanical polishing (CMP) method for gate last process'20138,389,359'Method for forming low resistance and uniform metal gate'20138,378,428'Metal gate structure of a semiconductor device'20138,373,199'Semiconductor device having a SiGe feature and a metal gate stack'20138,372,706'Semiconductor device fabrication method including hard mask and sacrificial spacer elements'20138,368,136'Integrating a capacitor in a metal gate last process'20138,368,170'Reducing device performance drift caused by large spacings between active regions'20138,367,515'Hybrid shallow trench isolation for high-k metal gate device improvement'20138,361,866'Modifying work function in PMOS devices by counter-doping'20138,349,678'Laterally diffused metal oxide semiconductor transistor with partially unsilicided source/drain'20138,349,680'High-k metal gate CMOS patterning method'20138,349,732'Implanted metal silicide for semiconductor device'20138,343,867'Method for main spacer trim-back'20138,334,572'Resistive device for high-k metal gate technology'20128,329,521'Method and device with gate structure formed over the recessed top portion of the isolation structure'20128,324,046'Poly resistor and poly eFuse design for replacement gate technology'20128,304,831'Method and apparatus of forming a gate'20128,304,840'Spacer structures of a semiconductor device'20128,304,842'Interconnection structure for N/P metal gates'20128,304,839'Poly resistor and poly eFuse design for replacement gate technology'20128,294,216'Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors'20128,286,114'3-dimensional device design layout'20128,258,584'Offset gate semiconductor device'20128,237,201'Layout methods of integrated circuits having unit MOS devices'20128,237,227'Dummy gate structure for gate last process'20128,216,888'Eliminating poly uni-direction line-end shortening using second cut'20128,202,776'Method for protecting a gate structure during contact formation'20128,193,586'Sealing structure for high-K metal gate'20128,183,644'Metal gate structure of a CMOS semiconductor device'20128,173,491'Standard cell architecture and methods with variable design rules'20128,153,498'Downsize polysilicon height for polysilicon resistor integration of replacement gate process'20128,143,131'Method of fabricating spacers in a strained semiconductor device'20128,143,137'Method of fabricating semiconductor device by thinning hardmask layers on frontside and backside of substrate'20128,125,051'Device layout for gate last process'20128,105,929'Gate control and endcap improvement'20128,105,891'Method for tuning a work function of high-K metal gate devices'20128,093,120'Integrating a first contact structure in a gate last process'20128,093,116'Method for N/P patterning in a gate last process'20128,058,119'Device scheme of HKMG gate-last process'20118,048,752'Spacer shape engineering for void-free gap-filling process'2011

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (174)· patent assignee history
2003–2015Based in Austin, TX, US· patent location history
2008–2018Based in Hsinchu, TW· patent location history
2011–2016Patents assigned to THEI KONG-BENG (43)· patent assignee history
2011–2015Patents assigned to CHUANG HARRY (38)· patent assignee history
2012–2018Patents assigned to ZHU MING (30)· patent assignee history
2013–2021Based in Singapore, SG· patent location history
2014–2020Based in Crescent, SG· patent location history
2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (162)· patent assignee history
2015–2020Based in Zhubei City, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG1742003–2016
TAIWAN SEMICONDUCTOR MFG CO LTD1622015–2021
THEI KONG-BENG432011–2016
CHUANG HARRYself382011–2015
ZHU MING302012–2018
Locations
LocationPatentsSpan
Singapore, SG1212013–2021
Hsinchu, TW982008–2018
Zhubei City, TW442015–2020
Austin, Texas, US302003–2015
Crescent, SG162014–2020