Inventor
Martin Langhammer
Inventor
Salisbury, GB
Overview
Patents· 226 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing54%
H03KPulse technique17%
H03MCoding9%
H04LTransmission of digital information, e.g. telegraphic communication9%
H03HImpedance networks, e.g. resonant circuits4%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy2%
G11CStatic stores1%
G06GAnalogue computers1%
G06NComputing arrangements based on specific computational models1%
H04BTransmission1%
PatentTitleYear
11,101,925Decomposable forward error correction202111,080,019Method and apparatus for performing synthesis for field programmable gate array embedded feature placement202111,016,733Continuous carry-chain packing202111,010,131Floating-point adder circuitry with subnormal support202111,010,134High radix subset code multiplier architecture202111,003,446Reduction operation mapping systems and methods202110,996,926Variable precision floating-point multiplier202110,970,042Integrated circuits with machine learning extensions202110,970,409Security RAM block with multiple partitions202110,942,706Implementation of floating-point trigonometric functions in an integrated circuit device202110,922,471High performance regularized network-on-chip architecture202110,871,946Methods for using a multiplier to support multiple sub-multiplication operations202010,872,130High performance QR decomposition systems and methods202010,873,332Adder circuitry for very large integers202010,867,090Method and apparatus for implementing an application aware system on a programmable logic device202010,838,695Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks202010,790,829Logic circuits with simultaneous dual function capability202010,761,805Reduced floating-point precision arithmetic circuitry202010,732,932Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extension202010,715,144Logic circuits with augmented arithmetic densities202010,678,510Denormalization in multi-precision floating-point arithmetic circuitry202010,649,731Integrated circuits with specialized processing blocks for performing floating-point fast fourier transforms and complex multiplication202010,613,831Methods and apparatus for performing product series operations in multiplier accumulator blocks202010,574,267Circuitry and methods for continuous parallel decoder operation202010,572,222Variable precision floating-point multiplier202010,521,194Mixed-precision floating-point arithmetic circuitry in specialized processing blocks201910,521,227Distributed double-precision floating-point addition201910,474,429Programmable device implementing fixed and floating point functionality in a mixed architecture201910,417,004Pipelined cascaded digital signal processing structures and methods201910,379,815Variable precision floating-point multiplier201910,374,636Circuit structure and method for high-speed forward error correction201910,340,920High performance FPGA addition201910,318,241Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks201910,237,066Multi-channel encryption and authentication201910,230,399Circuitry and method for decomposable decoder201910,218,386Methods and apparatus for performing variable and breakout Reed Solomon encoding201910,210,919Integrated circuits with embedded double-clocked components201910,181,864Methods and apparatus for performing reed-solomon encoding201910,175,944Mixed-precision floating-point arithmetic circuitry in specialized processing blocks201910,164,660Syndrome-based Reed-Solomon erasure decoding circuitry201810,140,091Integrated circuits with specialized processing blocks for performing floating-point fast fourier transforms and complex multiplication201810,127,013Specialized processing blocks with fixed-point and floating-point structures201810,110,233Methods for specifying processor architectures for programmable integrated circuits201810,101,966Digital signal processing blocks with embedded arithmetic circuits201810,095,647Accelerator architecture on a programmable platform201810,075,189Techniques for variable forward error correction201810,073,676Reduced floating-point precision arithmetic circuitry201810,061,579Distributed double-precision floating-point addition201810,055,195Variable precision floating-point adder and subtractor201810,042,607Variable precision floating-point multiplier201810,042,606Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks201810,037,189Distributed double-precision floating-point multiplication201810,037,192Methods and apparatus for performing product series operations in multiplier accumulator blocks201810,031,846Transposition of two-dimensional arrays using single-buffering201810,031,752Distributed double-precision floating-point addition201810,020,812Techniques for variable latency redundancy20189,992,053Multi-channel, multi-lane encryption circuitry and methods20189,966,933Pipelined systolic finite impulse response filter20189,954,553Circuitry and methods for continuous parallel decoder operation20189,934,841Systems and methods for refreshing data in memory circuits20189,787,290'Resource-saving circuit structures for deeply pipelined systolic finite impulse response filters'20179,747,110'Pipelined cascaded digital signal processing structures and methods'20179,696,991'Fixed-point and floating-point optimization'20179,684,488'Combined adder and pre-adder for high-radix multiplier circuit'20179,619,207'Circuitry and methods for implementing Galois-field reduction'20179,613,232'Digital signal processing blocks with embedded arithmetic circuits'20179,606,608'Low power optimizations for a floating point multiplier'20179,600,278'Programmable device using fixed and configurable logic to implement recursive trees'20179,594,928'Multi-channel, multi-lane encryption circuitry and methods'20179,583,218'Configurable register circuitry for error detection and recovery'20179,582,686'Unique secure serial ID'20179,575,725'Specialized processing block with embedded pipelined accumulator circuitry'20179,552,190'Fused floating point datapath with correct rounding'20179,552,189'Embedded floating-point operator circuitry'20179,553,591'Hybrid architecture for signal processing'20179,519,807'Hash generation circuitry and methods for multi-channel, multi-lane encryption and authentication'20169,507,565'Programmable device implementing fixed and floating point functionality in a mixed architecture'20169,395,953'Large multiplier for programmable logic device'20169,391,781'Systems and methods for intermediate message authentication in a switched-path network'20169,379,687'Pipelined systolic finite impulse response filter'20169,348,795'Programmable device using fixed and configurable logic to implement floating-point rounding'20169,348,557'Fused floating point datapath with correct rounding'20169,344,113'Lempel Ziv compression architecture'20169,337,844'Generalized parallel counter structures in logic devices'20169,331,714'Circuit structure and method for high-speed forward error correction'20169,235,540'Flexible high speed forward error correction (FEC) physical medium attachment (PMA) and physical coding sublayer (PCS) connection system'20169,208,357'FPGA configuration bitstream protection using multiple keys'20159,207,908'Digital signal processing blocks with embedded arithmetic circuits'20159,207,909'Polynomial calculations optimized for programmable integrated circuit device structures'20159,189,200'Multiple-precision processing block in a programmable integrated circuit device'20159,170,985'Bidirectional fast fourier transform in an integrated circuit device'20159,172,537'Array encryption core'20159,170,775'Flexible accumulator in digital signal processing circuitry'20159,164,728'Ternary DSP block'20159,118,349'Continuous parallel cyclic BCH decoding architecture'20159,098,332'Specialized processing block with fixed- and floating-point structures'20159,069,624'Systems and methods for DSP block enhancement'20159,063,870'Large multiplier for programmable logic device'20159,054,859'FPGA configuration bitstream encryption using modified key'20159,053,045'Computing floating-point polynomials in an integrated circuit device'20159,032,277'Parallel low and asymmetric rate Reed Solomon coding'20158,996,600'Specialized processing block for implementing floating-point multiplier with subnormal operation support'20158,977,938'Parallel decomposition of Reed Solomon umbrella codes'20158,959,137'Implementing large multipliers in a programmable integrated circuit device'20158,949,298'Computing floating-point polynomials in an integrated circuit device'20158,898,551'Reduced matrix Reed-Solomon encoding'20148,886,695'Normalization of floating point operations in a programmable integrated circuit device'20148,886,696'Digital signal processing circuitry with redundancy and ability to support larger multipliers'20148,862,650'Calculation of trigonometric functions in an integrated circuit device'20148,856,201'Mixed-mode multiplier using hard and soft logic circuitry'20148,825,729'Power and bandwidth efficient FFT for DDR memory'20148,826,038'FPGA configuration bitstream protection using multiple keys'20148,812,573'Calculation of trigonometric functions in an integrated circuit device'20148,812,819'Methods and apparatus for reordering data signals in fast fourier transform systems'20148,805,916'Digital signal processing circuitry with redundancy and bidirectional data paths'20148,805,911'Cholesky decomposition in an integrated circuit device'20148,788,562'Large multiplier for programmable logic device'20148,751,551'Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry'20148,750,503'FPGA configuration bitstream encryption using modified key'20148,713,081'Look up table (LUT) structure supporting exclusive OR (XOR) circuitry configured to allow for generation of a result using quaternary adders'20148,707,143'Multiplication-based reed-solomon encoding architecture'20148,706,790'Implementing mixed-precision floating-point operations in a programmable integrated circuit device'20148,681,974'Array encryption core'20148,670,561'Method and apparatus for limiting use of IP'20148,667,045'Generalized parallel counter structures in logic devices'20148,650,231'Configuring floating point operations in a programmable device'20148,649,518'Implementing CSA cryptography in an integrated circuit device'20148,650,230'Logic structures and methods supporting pipelined multi-operand adders'20148,645,712'Electronic circuit design copy protection'20148,645,451'Double-clocked specialized processing block in an integrated circuit device'20148,645,449'Combined floating point adder and subtractor'20148,626,815'Configuring a programmable integrated circuit device to perform matrix multiplication'20148,621,331'Continuous parallel cyclic BCH decoding architecture'20138,620,977'Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry'20138,620,980'Programmable device with specialized multiplier blocks'20138,615,543'Saturation and rounding in multiply-accumulate blocks'20138,615,617'Lempel ziv compression architecture'20138,612,772'Security core using soft key'20138,601,044'Discrete Fourier Transform in an integrated circuit device'20138,589,463'Calculation of trigonometric functions in an integrated circuit device'20138,577,951'Matrix operations in an integrated circuit device'20138,566,616'Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like'20138,549,055'Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry'20138,539,014'Solving linear matrices in an integrated circuit device'20138,539,016'QR decomposition in an integrated circuit device'20138,510,357'Logic structures and methods supporting pipelined multi-operand adders'20138,510,354'Calculation of trigonometric functions in an integrated circuit device'20138,484,275'Reordering discrete fourier transform outputs'20138,484,265'Angular range reduction in an integrated circuit device'20138,482,312'Logic structures for ternary addition in logic devices'20138,468,192'Implementing multipliers in a programmable integrated circuit device'20138,447,798'Look up table (LUT) structure supporting exclusive or (XOR) circuitry configured to allow for generation of a result using quaternary adders'20138,433,930'One-time programmable memories for key storage'20138,412,756'Multi-operand floating point operations in a programmable integrated circuit device'20138,396,914'Matrix decomposition in an integrated circuit device'20138,392,488'Logic structures and methods supporting pipelined multi-operand adders'20138,386,553'Large multiplier for programmable logic device'20138,364,738'Programmable logic device with specialized functional block'20138,363,833'FPGA configuration bitstream encryption using modified key'20138,347,192'Parallel finite field vector operators'20138,300,805'AES core with independent inputs and outputs'20128,301,681'Specialized processing block for programmable logic device'20128,266,199'Specialized processing block for programmable logic device'20128,266,198'Specialized processing block for programmable logic device'20128,255,448'Implementing division in a programmable integrated circuit device'20128,244,789'Normalization of floating point operations in a programmable integrated circuit device'20128,209,545'FPGA configuration bitstream protection using multiple keys'20128,082,283'Arrangement of 3-input LUT\'S to implement 4:2 compressors for multiple operand arithmetic'20118,041,759'Specialized processing block for programmable logic device'20117,991,812'Programmable logic devices with function-specific blocks'20117,984,292'FPGA configuration bitstream encryption using modified key'20117,948,267'Efficient rounding circuits and methods in configurable integrated circuit devices'20117,937,510'Lempel Ziv compression architecture'20117,930,336'Large multiplier for programmable logic device'20117,865,541'Configuring floating point operations in a programmable logic device'20117,836,117'Specialized processing block for programmable logic device'20107,822,799'Adder-rounder circuitry for specialized processing block in programmable logic device'20107,818,584'One-time programmable memories for key storage'20107,801,937'Method and apparatus for implementing a look-ahead for low radix Montgomery multiplication'20107,752,407'Security RAM block'20107,734,043'Encryption key obfuscation and storage'20107,725,738'FPGA configuration bitstream protection using multiple keys'20107,698,358'Programmable logic device with specialized functional block'20107,660,841'Flexible accumulator in digital signal processing circuitry'20107,606,362'FPGA configuration bitstream encryption using modified key'20097,590,676'Programmable logic device with specialized multiplier blocks'20097,587,443'Digital signal processor with efficient multi-modal multiplier'20097,587,438'DSP processor architecture with write datapath word conditioning and analysis'20097,587,614'Encryption algorithm optimized for FPGAs'20097,565,388'Logic cell supporting addition of three binary words'20097,484,081'Method and apparatus for protecting designs in SRAM-based programmable logic devices'20097,467,176'Saturation and rounding in multiply-accumulate blocks'20087,437,401'Multiplier-accumulator block mode splitting'20087,346,644'Devices and methods with programmable logic and digital signal processing regions'20087,302,460'Arrangement of 3-input LUT\'s to implement 4:2 compressors for multiple operand arithmetic'20077,287,051'Multi-functional digital signal processing circuitry'20077,260,154'Method and apparatus for implementing a multiple constraint length Viterbi decoder'20077,256,715'Data compression using dummy codes'20077,230,451'Programmable logic device with routing channels'20077,228,531'Methods and apparatus for optimizing a processor core on a programmable chip'20077,216,139'Programmable logic device including multipliers and configurations thereof to reduce resource utilization'20077,173,985'Method and apparatus for implementing a Viterbi decoder'20077,142,010'Programmable logic device including multipliers and configurations thereof to reduce resource utilization'20067,142,011'Programmable logic device with routing channels'20067,119,576'Devices and methods with programmable logic and digital signal processing regions'20067,109,895'High performance Lempel Ziv compression architecture'20067,109,753'Programmable logic device with routing channels'20067,084,664'Integrated circuits with reduced interconnect overhead'20067,035,356'Efficient method for traceback decoding of trellis (Viterbi) codes'20067,024,446'Circuitry for arithmetically accumulating a succession of arithmetic values'20067,003,544'Method and apparatus for generating a squared value for a signed binary number'20066,987,401'Compare, select, sort, and median-filter apparatus in programmable logic devices and associated methods'20066,978,287'DSP processor architecture with write datapath word conditioning and analysis'20056,958,624'Data latch with low-power bypass mode'20056,937,062'Specialized programmable logic region with low-power mode'20056,781,408'Programmable logic device with routing channels'20046,771,094'Devices and methods with programmable logic and digital signal processing regions'20046,714,042'Specialized programmable logic region with low-power mode'20046,693,455'Programmable logic device including multipliers and configurations thereof to reduce resource utilization'20046,628,140'Programmable logic devices with function-specific blocks'20036,586,966'Data latch with low-power bypass mode'20036,566,906'Specialized programmable logic region with low-power mode'20036,556,044'Programmable logic device including multipliers and configurations thereof to reduce resource utilization'20036,538,470'Devices and methods with programmable logic and digital signal processing regions'20036,400,290'Normalization implementation for a logmap decoder'20026,317,771'Method and apparatus for performing digital division'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2021Patents assigned to ALTERA CORP (199)· patent assignee history
2003–2009Based in Poole, GB· patent location history
2003–2011Based in Sandbanks, GB· patent location history
2004–2021Based in Salisbury, GB· patent location history
2006–2021Based in Alderbury, GB· patent location history
2009–2015Based in Wiltshire, GB· patent location history
2011–2017Patents assigned to LANGHAMMER MARTIN (65)· patent assignee history
2012–2014Patents assigned to STREICHER KEONE (7)· patent assignee history
2012–2017Patents assigned to JOYCE JUJU (5)· patent assignee history
2018–2021Patents assigned to INTEL CORP (26)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 199 | 2001–2021 |
| LANGHAMMER MARTINself | 65 | 2011–2017 |
| INTEL CORP | 26 | 2018–2021 |
| STREICHER KEONE | 7 | 2012–2014 |
| JOYCE JUJU | 5 | 2012–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Salisbury, GB | 121 | 2004–2021 |
| Alderbury, GB | 68 | 2006–2021 |
| Poole, GB | 13 | 2003–2009 |
| Wiltshire, GB | 11 | 2009–2015 |
| Sandbanks, GB | 4 | 2003–2011 |