Inventor
Gregory Burd
Inventor
San Jose, CA, US
Overview
Patents· 325 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Mprimary
H03MCoding39%
G11BInformation storage based on relative movement between record carrier and transducer27%
G06FElectric digital data processing13%
H04LTransmission of digital information, e.g. telegraphic communication11%
G11CStatic stores9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
B82YSpecific uses or applications of nanostructures0%
H04BTransmission0%
H04NPictorial communication, e.g. television0%
PatentTitleYear
10,365,966Methods and systems for wordline based encoding and decoding in NAND flash201910,261,707Decoder memory sharing201910,255,944Systems and methods for reading and decoding encoded data from a storage device201910,224,063Method and system for writing and reading closely-spaced data tracks201910,186,296Error correction for storage devices20199,953,678Servo gray code quality detector20189,946,599Systems and methods for enhanced data access to a hard disk drive with caching20189,922,678'Error correction for storage devices'20189,837,110Digital data driven position error signal for magnetic recording20179,786,319'Codes and techniques for magnetic recording'20179,734,848'Method and system for writing and reading closely-spaced data tracks'20179,672,853'Digital data driven position error signal for magnetic recording'20179,535,477'Power management of iterative data processing systems'20179,490,849'Systems and methods for configuring product codes for error correction in a hard disk drive'20169,467,170'NAND flash memory systems with efficient soft information interface'20169,443,551'Method and system for writing and reading closely-spaced data tracks'20169,438,276'Method and apparatus for improved performance of iterative decoders on channels with memory'20169,418,690'Repeated runout (RRO) zero phase start (ZPS)'20169,413,567'Systems and methods for finite impulse response adaptation for gain and phase control'20169,397,698'Methods and apparatus for error recovery in memory systems employing iterative codes'20169,391,639'LDPC multi-decoder architectures'20169,384,767'Generating position error signal based on data tracks for rotating magnetic data storage'20169,368,235'Defect detection using pattern matching on detected data'20169,363,036'Methods and apparatus for defect detection and correction via nonbinary iterative decoding'20169,350,534'Method and apparatus for pipelined byte substitution in encryption and decryption'20169,323,611'Systems and methods for multi-stage soft input decoding'20169,311,937'Systems and methods for calibrating read and write operations in two dimensional magnetic recording'20169,294,130'Quasi-cyclic low-density parity-check (QC-LDPC) encoder'20169,256,492'Iterative decoding systems using noise-biasing'20169,256,487'Optimizing error floor performance of finite-precision layered decoders of low-density parity-check (LDPC) codes'20169,251,380'Method and storage device for isolating and preventing access to processor and memory used in decryption of text'20169,214,964'Systems and methods for configuring product codes for error correction in a hard disk drive'20159,201,731'Error correction for storage devices'20159,202,515'Apparatus and method for adjusting a phase of a data clock signal using a predetermined bit pattern'20159,189,315'Channel quality monitoring and method for qualifying a storage channel using an iterative decoder'20159,183,942'Inter-cell interference cancellation'20159,160,368'Systems and methods for near-codeword detection and correction on the fly'20159,160,373'Systems and methods for joint decoding of sector and track error correction codes'20159,152,558'Mapping different portions of data to different pages of multi-level non-volatile memory'20159,153,323'Systems and methods for generating soft information in NAND flash'20159,147,419'Generating position error signal based on data tracks for magnetic data storage'20159,147,491'Adaptive read and write systems and methods for memory cells'20159,142,312'Adapting read reference voltage in flash memory device'20159,143,168'Method and system for removing interference caused by servo data from user data'20159,129,654'Systems and methods for data-path protection'20159,123,369'Method and apparatus for determining position of multiple drive heads'20159,117,472'Processing a data signal with an embedded position signal'20159,112,532'QC-LDPC decoder with list-syndrome decoding'20159,098,411'Methods and apparatus for defect detection and correction via iterative decoding algorithms'20159,088,300'Cyclic redundancy check for out-of-order codewords'20159,075,745'System and method for adding a drive to a storage system having multiple drives'20159,077,501'Systems and methods for detecting cycle slip and/or framing error'20159,065,623'Mixed mapping for rate compatible trellis coded modulation'20159,053,742'Repeated runout (RRO) zero phase start (ZPS)'20159,048,879'Error correction system using an iterative product code'20159,048,871'LDPC multi-decoder architectures'20159,036,288'Method and system for reading closely-spaced data tracks'20159,037,875'Key generation techniques'20159,025,262'Systems and methods for asymmetry detection based on a synchronization mark'20159,019,638'Systems and methods for performing timing acquisition in a read/write channel module'20159,013,819'Write clock phase tracking for magnetic recording device'20159,009,574'Identification and mitigation of hard errors in memory systems'20159,009,560'Apparatus for encoding and decoding using sparse matrices'20159,002,002'Method and apparatus of high speed encryption and decryption'20159,003,267'Power consumption in LDPC decoder for low-power applications'20158,988,808'Write clock rephase for magnetic recording device'20158,988,800'Error correction for storage devices'20158,989,252'Methods and apparatus for power efficient iterative equalization'20158,984,378'Systems and methods for performing multi-state bit flipping in an LDPC decoder'20158,977,941'Iterative decoder systems and methods'20158,977,813'Implementing RAID in solid state memory'20158,971,122'Group based read reference voltage management in flash memory'20158,964,323'System and method for detecting and correcting shift in a DC level of an input signal'20158,947,810'Bit-locked interface for magnetic recording'20158,943,381'Systems and methods for performing bit flipping in an LDPC decoder'20158,937,778'Methods and apparatus for performing track-level based data coding'20158,938,660'Systems and methods for detection and correction of error floor events in iterative systems'20158,935,601'Post-processing methodologies in decoding LDPC codes'20158,935,600'Modification of decoder operating mode based on a probability of non-standard errors in concatenated decoding systems'20158,929,147'Determining threshold voltage distribution in flash memory'20158,924,747'Power management of iterative data processing systems'20148,913,437'Inter-cell interference cancellation'20148,910,009'Method and apparatus for enhancing error detection in data transmission'20148,910,013'Methods and apparatus for providing multi-layered coding for memory devices'20148,910,024'Systems and methods for encoding data to meet an output constraint'20148,898,553'Log-likelihood-ratio (LLR) table calibration'20148,896,956'Method and system for reading closely-spaced data tracks'20148,891,195'Method and system for compensating for track squeeze'20148,887,032'Defect detection and correction via monitoring of syndromes and bit flips in decoder'20148,887,033'Channel quality monitoring and method for qualifying a storage channel using an iterative decoder'20148,879,193'Method and system for compensating for adjacent tracks during reading of data'20148,879,185'Disk synchronous write architecture for bit-patterned recording'20148,873,181'Method and apparatuses for synchronizing writing of data with a pattern of bit islands of media'20148,868,999'Systems and methods for erasure correction of iterative codes'20148,861,114'Method and system for compensating for adjacent tracks during reading of data'20148,862,970'Low power LDPC decoding under defects/erasures/puncturing'20148,862,965'Decoding failure management'20148,837,074'Method and system for compensating for track squeeze'20148,825,945'Mapping different portions of data to different pages of multi-level non-volatile memory'20148,819,530'Iterative decoder memory arrangement'20148,817,400'Storage device interface for shingled magnetic recording system'20148,812,929'Detecting insertion/deletion using LDPC code'20148,810,938'Systems and methods for performing timing acquisition on an expected preamble of a read signal'20148,812,939'Soft decoding systems and methods for flash based memory systems'20148,806,299'Method and apparatus for compressing data sectors in storage drive'20148,804,259'Systems and methods for revising data in a signal read from a storage medium according to a calculated gain'20148,799,742'QC-LDPC decoder with list-syndrome decoding'20148,799,556'Adaptive read and write systems and methods for memory cells'20148,799,737'Soft-information modification in concatenated decoding systems'20148,786,979'Self servo write process for discrete track media'20148,788,916'Architecture and control of reed-solomon error-correction decoding'20148,788,911'Parity insertion for inner architecture'20148,779,847'Systems and methods for finite impulse response adaptation for gain and phase control'20148,773,792'Systems and methods for inter-track interference cancellation in magnetic recording channels'20148,769,380'Methods and apparatus for error recovery in memory systems employing iterative codes'20148,769,382'Optimizing error floor performance of finite-precision layered decoders of low-density parity-check (LDPC) codes'20148,760,785'Write clock phase tracking for magnetic recording device'20148,762,824'Error pattern generation for trellis-based detection and/or decoding'20148,762,809'LDPC codes and expansion method'20148,762,817'Method and apparatus for determining the start of a data field in a data frame'20148,755,140'Write clock rephase for magnetic recording device'20148,756,479'LDPC multi-decoder architectures'20148,755,139'System with servo clock and write clock based phase estimation for discontinuous media writing'20148,750,498'Method and apparatus for encoding data in accordance with the advanced encryption standard (AES)'20148,745,468'Iterative decoding systems using noise-biasing'20148,739,003'Method and apparatus for decoding a data sector including user data and non-user data'20148,739,009'Methods and apparatus for defect detection and correction via iterative decoding algorithms'20148,730,609'DC shift detection and correction'20148,730,605'Write zero phase start for phase synchronization in bit patterned recording'20148,725,929'Adaptive read and write systems and methods for memory cells'20148,725,944'Implementing raid in solid state memory'20148,700,973'Post-processing decoder of LDPC codes for improved error floors'20148,693,122'Method and system for compensating for adjacent tracks during reading of data'20148,693,275'Method and apparatus for calibrating a read/write channel in a memory arrangement'20148,693,118'Timing acquisition robust to inter-track-interference'20148,693,124'Bit-locked interface for magnetic recording'20148,694,868'Systems and methods for performing multi-state bit flipping in an LDPC decoder'20148,687,304'Sensor-aided patterned magnetic media synchronization systems'20148,683,274'Error correction coding for varying signal-to-noise ratio channels'20148,683,277'Defect detection using pattern matching on detected data'20148,681,564'Systems and methods for generating soft information in NAND flash'20148,675,414'Group based read reference voltage management in flash memory'20148,667,361'Systems and methods for performing bit flipping in an LDPC decoder'20148,661,325'Iterative decoder systems and methods'20148,659,942'Adapting read reference voltage in flash memory device'20148,654,470'Clock frequency synchronization for magnetic recording device'20148,649,120'Systems and methods for gain compensation and re-timing in magnetic recording channels'20148,638,513'Method and system for compensating for adjacent tracks during reading of data'20148,635,515'Multi-parity tensor-product code for data channel'20148,635,513'Architecture and control of Reed-Solomon list decoding'20148,627,167'Methods and apparatus for providing multi-layered coding for memory devices'20148,625,215'Method and system for compensating for adjacent tracks during writing of data'20148,625,369'Determining threshold voltage distribution in flash memory'20148,627,179'Split sector recovery method'20148,625,228'Method and system for compensating for track squeeze'20148,621,334'Log-likelihood-ratio (LLR) table calibration'20138,612,837'BM/LLR computations for multi-dimensional TCM/BCM codes'20138,601,328'Systems and methods for near-codeword detection and correction on the fly'20138,599,508'Method and system for compensating for adjacent tracks during reading of data'20138,601,354'Methods and apparatus for identification of likely errors in data blocks'20138,583,981'Concatenated codes for holographic storage'20138,578,251'Power saving area-efficient hybrid BCH coding system'20138,543,838'Cryptographic module with secure processor'20138,543,886'Parity insertion for inner architecture'20138,543,894'Channel quality monitoring and method for qualifying a storage channel using an iterative decoder'20138,537,482'Systems and methods for inter-track interference cancellation in magnetic recording channels'20138,531,903'Method and apparatus for calibrating a read/write channel in a memory arrangement'20138,531,792'Self servo write process for discrete track media'20138,533,496'Power management of iterative data processing systems'20138,527,850'Architecture and control of reed-solomon error identification and evaluation'20138,522,123'Iterative decoder memory arrangement'20138,516,332'Methods and algorithms for joint channel-code decoding of linear block codes'20138,508,878'Write clock phase tracking for magnetic recording device'20138,508,879'Write clock rephase for magnetic recording device'20138,504,887'Low power LDPC decoding under defects/erasures/puncturing'20138,494,155'Method and apparatus of high speed encryption and decryption'20138,495,479'Defect detection and correction via monitoring of syndromes and bit flips in decoder'20138,495,458'Systems and methods for multistage error correction'20138,489,960'LDPC codes and expansion method'20138,489,977'Low-density parity check codes for holographic storage'20138,484,527'Systems and methods for achieving higher coding rate using parity interleaving'20138,484,537'Systems and methods for data-path protection'20138,484,531'Post-processing decoder of LDPC codes for improved error floors'20138,477,444'Clock frequency synchronization for magnetic recording device'20138,473,824'Quasi-cyclic low-density parity-check (QC-LDPC) encoder'20138,458,557'Interleaved error correction coding for channels with non-uniform signal-to-noise ratios'20138,441,750'Method and system for compensating for adjacent tracks during reading of data'20138,438,461'Power consumption in LDPC decoder for low-power applications'20138,423,870'Method and apparatus for determining the start of a data field in a data frame'20138,423,789'Key generation techniques'20138,418,031'Systems and methods for encoding data to meet an output constraint'20138,407,570'Decoding methods and apparatus for fractional multidimensional trellis coded modulation systems'20138,407,562'Systems and methods for compressing data in non-volatile semiconductor memory drives'20138,402,351'Error correction coding with nuisance data'20138,402,217'Implementing RAID in solid state memory'20138,402,345'Methods and apparatus for providing multilevel coset coding and probabilistic error correction'20138,397,139'Method and apparatus for processing nuisance data'20138,395,858'Methods and apparatus for performing interpolated timing recovery'20138,392,809'Log-likelihood-ratio (LLR) table calibration'20138,386,889'Drive replacement techniques for RAID systems'20138,381,082'Power-saving area-efficient hybrid BCH coding system'20138,363,478'Group based read reference voltage management in flash memory'20138,363,501'Method and apparatus for calibrating a read/write channel in a memory arrangement'20138,351,258'Adapting read reference voltage in flash memory device'20138,347,195'Systems and methods for near-codeword detection and correction on the fly'20138,331,169'Determining threshold voltage distribution in flash memory'20128,331,050'Patterned magnetic media synchronization systems'20128,327,244'BM/LLR computations for multi-dimensional TCM/BCM codes'20128,321,763'Split sector recovery method'20128,321,769'Multi-parity tensor-product code for data channel'20128,316,287'Low-density parity check codes for holographic storage'20128,312,354'Method and apparatus for improved performance of iterative decoders on channels with memory'20128,312,341'Interleaved error correction coding for channels with non-uniform SNRs'20128,307,268'Iterative decoder systems and methods'20128,301,984'QC-LDPC decoder with list-syndrome decoding'20128,300,344'Data synchronization for bit insertion or deletion'20128,300,339'Method and system for compensating for adjacent tracks during reading of data'20128,296,635'Architecture and control of Reed-Solomon error-correction decoding'20128,296,637'Channel quality monitoring and method for qualifying a storage channel using an iterative decoder'20128,291,290'Methods and algorithms for joint channel-code decoding of linear block codes'20128,291,292'Optimizing error floor performance of finite-precision layered decoders of low-density parity-check (LDPC) codes'20128,281,213'LDPC codes and expansion method'20128,255,764'Embedded parity coding for data storage'20128,255,763'Error correction system using an iterative product code'20128,255,765'Embedded parity coding for data storage'20128,245,118'Architecture and control of reed-solomon error identification and evaluation'20128,239,731'Methods and apparatus for providing multilevel coset coding and probabilistic error correction'20128,230,312'Iterative decoder memory arrangement'20128,225,185'RS codec architecture that combines a compact encoder and serial BMA'20128,225,148'Systems and methods for achieving higher coding rate using parity interleaving'20128,219,878'Post-processing decoder of LDPC codes for improved error floors'20128,219,894'Architecture and control of reed-solomon error-correction decoding'20128,219,868'Quasi-cyclic low-density parity-check (QC-LDPC) encoder'20128,209,580'Error correction coding for varying signal-to-noise ratio channels'20128,190,963'Error correction using error detection codes'20128,181,084'Detecting insertion/deletion using LDPC code'20128,176,401'Decoding methods and apparatus for fractional multidimensional trellis coded modulation systems'20128,171,309'Secure memory controlled access'20128,166,370'Efficient RAID ECC controller for RAID systems'20128,155,308'Advanced encryption system hardware architecture'20128,156,400'Embedded parity coding for data storage'20128,149,959'Enhancements of soft decoders and detectors on asymmetric channels'20128,145,983'Methods and apparatus for identification of likely errors in data blocks'20128,140,943'Parity insertion for inner architecture'20128,136,016'Split sector recovery method'20128,132,083'Architecture and control of reed-solomon list decoding'20128,132,082'Architecture and control of Reed-Solomon error-correction decoding'20128,127,209'QC-LDPC decoder with list-syndrome decoding'20128,106,799'Data compression and decompression using parallel processing'20128,086,945'Tensor product codes containing an iterative code'20118,077,520'Determining threshold voltage distribution in flash memory'20118,074,151'Correcting errors in disk drive read back signals by iterating with the reed-solomon decoder'20118,069,391'Error correction using error detection codes'20118,054,207'Enumerative DC-RLL constrained coding'20118,049,983'Methods and apparatus for performing interpolated timing recovery'20118,045,285'Data synchronization for bit insertion or deletion'20118,044,832'Interleaver for turbo equalization'20118,042,027'BM/LLR computation for multi-dimensional TCM/BCM'20118,040,953'Reliability metric generation for trellis-based detection and/or decoding'20118,036,377'Method and apparatus of high speed encryption and decryption'20118,028,216'Embedded parity coding for data storage'20118,019,020'Binary decoding for correlated input information'20118,015,224'Entropy source for random number generation'20118,009,068'Filter driven DC-free code'20117,984,367'Method for iterative decoding in the presence of burst errors'20117,979,774'Error correction coding for varying quality channels'20117,978,100'Encoding and decoding methods using generalized concatenated codes (GCC)'20117,962,827'Systems and methods for achieving higher coding rate using parity interleaving'20117,941,590'Adaptive read and write systems and methods for memory cells'20117,936,630'Method and apparatus for calibrating a read/write channel in a memory arrangement'20117,934,143'Parity insertion for inner architecture'20117,917,836'Detection in the presence of media noise'20117,911,364'Interleaver for turbo equalization'20117,876,860'Enhancements of soft decoders and detectors on asymmetric channels'20117,861,131'Tensor product codes containing an iterative code'20107,855,665'Enumerative DC-RLL constrained coding'20107,840,878'Systems and methods for data-path protection'20107,827,461'Low-density parity-check decoder apparatus'20107,801,254'Address generator for LDPC encoder and decoder and method thereof'20107,782,232'Encoding and decoding methods using generalized concatenated codes (GCC)'20107,774,688'Hardware efficient decoding system for Bose, Ray-Chaudhuri, Hocquenghem (BCH) product codes'20107,774,675'LDPC codes and expansion method'20107,773,329'Correcting errors in a disk drive read back signals by iterating with the Reed-Solomon decoder'20107,765,458'Error pattern generation for trellis-based detection and/or decoding'20107,760,822'Address generator for LDPC encoder and decoder and method thereof'20107,751,505'LDPC encoder and encoder and method thereof'20107,752,523'Reduced-complexity decoding of parity check codes'20107,751,138'Correcting errors in disk drive read back signals by iterating with the Reed-Solomon decoder'20107,689,893'Iterative reed-solomon error-correction decoding'20107,685,494'Error correction coding for varying signal-to-noise ratio channels'20107,667,626'Enumerative DC-RLL constrained coding'20107,661,058'Efficient raid ECC controller for raid systems'20107,657,823'Efficient RAID ECC controller for RAID systems'20107,649,793'Channel estimation for multi-level memories using pilot signals'20107,623,048'DC-free codes'20097,590,923'Architecture and control of Reed-Solomon error identification and evaluation'20097,590,924'Architecture and control of Reed-Solomon list decoding'20097,583,751'LDPC encoder method thereof'20097,580,485'Address generator for LDPC encoder and decoder and method thereof'20097,571,372'Methods and algorithms for joint channel-code decoding of linear block codes'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2019Patents assigned to MARVELL INT LTD (282)· patent assignee history
2003–2019Based in San Jose, CA, US· patent location history
2005–2010Based in Santa Clara, CA, US· patent location history
2010–2019Patents assigned to MARVELL WORLD TRADE LTD (41)· patent assignee history
2011–2016Patents assigned to BURD GREGORY (133)· patent assignee history
2011–2015Patents assigned to WU ZINING (53)· patent assignee history
2012–2015Patents assigned to VARNICA NEDELJKO (35)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MARVELL INT LTD | 282 | 2003–2019 |
| BURD GREGORYself | 133 | 2011–2016 |
| WU ZINING | 53 | 2011–2015 |
| MARVELL WORLD TRADE LTD | 41 | 2010–2019 |
| VARNICA NEDELJKO | 35 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 317 | 2003–2019 |
| Santa Clara, California, US | 8 | 2005–2010 |