Inventor

Casey Scott

Inventor
Dresden, DE

Overview

13→
Patents
2010–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 13 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices48%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G01KMeasuring temperature4%
H01LSemiconductor devices4%
H10BElectronic memory devices4%
H10NElectric solid-state devices not otherwise provided for4%
PatentTitleYear
9,450,073'SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto'20168,652,913'Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss'20148,530,894'Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions'20138,373,244'Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure'20138,334,569'Transistor with embedded Si/Ge material having enhanced across-substrate uniformity'20128,227,266'Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions'20128,212,184'Cold temperature control in a semiconductor device'20128,183,100'Transistor with embedded SI/GE material having enhanced across-substrate uniformity'20128,138,050'Transistor device comprising an asymmetric embedded semiconductor alloy'20128,093,634'In situ formed drain and source regions in a silicon/germanium containing transistor device'20127,897,451'Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors'20117,811,876'Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor device'20107,713,763'Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2014Patents assigned to GLOBALFOUNDRIES INC (7)· patent assignee history
2010–2016Patents assigned to ADVANCED MICRO DEVICES INC (6)· patent assignee history
2010–2016Based in Dresden, DE· patent location history
2012–2016Patents assigned to SCOTT CASEY (10)· patent assignee history
2012–2016Patents assigned to WEI ANDY (7)· patent assignee history
2012–2013Patents assigned to MOWRY ANTHONY (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SCOTT CASEYself102012–2016
GLOBALFOUNDRIES INC72010–2014
WEI ANDY72012–2016
ADVANCED MICRO DEVICES INC62010–2016
MOWRY ANTHONY52012–2013
Locations
LocationPatentsSpan
Dresden, DE132010–2016