Inventor
Birendra N. Agarwala
Inventor
Hopewell Junction, NY, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1051%
H05KPrinted circuits17%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
G01RMeasuring electric variables9%
H10DInorganic electric semiconductor devices6%
Y10TTechnical subjects covered by former us classification6%
PatentTitleYear
8,466,056'Method of forming metal interconnect structures in ultra low-k dielectrics'20137,692,439'Structure for modeling stress-induced degradation of conductive interconnects'20107,639,032'Structure for monitoring stress-induced degradation of conductive interconnects'20097,470,613'Dual damascene multi-level metallization'20087,397,260'Structure and method for monitoring stress-induced degradation of conductive interconnects'20087,279,411'Process for forming a redundant structure'20077,224,063'Dual-damascene metallization interconnection'20077,163,883'Edge seal for a semiconductor device'20077,138,714'Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines'20066,972,209'Stacked via-stud with improved reliability in copper metallurgy'20056,825,561'Structure and method for eliminating time dependent dielectric breakdown failure of low-k material'20046,734,090'Method of making an edge seal for a semiconductor device'20046,271,599'Wire interconnect structure for electrically and mechanically connecting an integrated circuit chip to a substrate'20016,111,321'Ball limiting metalization process for interconnection'20006,033,939'Method for providing electrically fusible links in copper interconnection'20005,376,584'Process of making pad structure for solder ball limiting metallurgy having reduced edge stress'19945,268,072'Etching processes for avoiding edge stress in semiconductor chip solder bumps'19935,251,806'Method of forming dual height solder interconnections'19935,130,779'Solder mass having conductive encapsulating arrangement'19924,985,310'Multilayered metallurgical structure for an electronic component'19914,970,570'Use of tapered head pin design to improve the stress distribution in the braze joint'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2013Patents assigned to IBM (21)· patent assignee history
1990–1991Based in Wappingers Falls, NY, US· patent location history
1992–2010Based in Hopewell Junction, NY, US· patent location history
2013Patents assigned to AGARWALA BIRENDRA (1)· patent assignee history
2013Patents assigned to NGUYEN DU (1)· patent assignee history
2013Patents assigned to RATHORE HAZARA (1)· patent assignee history
2013Based in Hopewell Jct., NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 21 | 1990–2013 |
| AGARWALA BIRENDRAself | 1 | 2013 |
| NGUYEN DU | 1 | 2013 |
| RATHORE HAZARA | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hopewell Junction, New York, US | 18 | 1992–2010 |
| Wappingers Falls, New York, US | 2 | 1990–1991 |
| Hopewell Jct., New York, US | 1 | 2013 |