Inventor
Kevin W. Gorman
Inventor
Fairfax, VT, US
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores40%
G01RMeasuring electric variables23%
G06FElectric digital data processing10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
E06BFixed or movable closures for openings in buildings, vehicles, fences or like enclosures in general, e.g. doors, windows, blinds, gates3%
F24FAir-conditioning3%
H01LSemiconductor devices3%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
8,872,322'Stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks'20148,853,847'Stacked chip module with integrated circuit chips having integratable and reconfigurable built-in self-maintenance blocks'20148,661,734'Window assembly with a sliding member and a security member having a ventilation portion'20148,582,351'Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability'20138,028,195'Structure for indicating status of an on-chip power supply system'20117,917,806'System and method for indicating status of an on-chip power supply system'20117,631,236'Hybrid built-in self test (BIST) architecture for embedded memory arrays and an associated method'20097,565,585'Integrated redundancy architecture and method for providing redundancy allocation to an embedded memory system'20097,518,918'Method and apparatus for repairing embedded memory in an integrated circuit'20097,472,325'Method for segmenting BIST functionality in an embedded memory array into remote lower-speed executable instructions and local higher-speed executable instructions'20087,444,564'Automatic bit fail mapping for embedded memories with clock multipliers'20087,401,281'Remote BIST high speed test and redundancy calculation'20086,956,415'Modular DLL architecture for generating multiple timings'20056,882,583'Method and apparatus for implementing DRAM redundancy fuse latches using SRAM'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2014Patents assigned to IBM (13)· patent assignee history
2005–2009Based in Milton, VT, US· patent location history
2009–2014Based in Fairfax, VT, US· patent location history
2013Patents assigned to ARSOVSKI IGOR (1)· patent assignee history
2013Patents assigned to BRACERAS GEORGE M (1)· patent assignee history
2014Patents assigned to BRITPLAS COMMERCIAL WINDOWS LTD (1)· patent assignee history
2014Patents assigned to EUROCELL PROFILES LTD (1)· patent assignee history
2014Based in Cheshire, GB· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 13 | 2005–2014 |
| ARSOVSKI IGOR | 1 | 2013 |
| BRACERAS GEORGE M | 1 | 2013 |
| BRITPLAS COMMERCIAL WINDOWS LTD | 1 | 2014 |
| EUROCELL PROFILES LTD | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fairfax, VT, US | 7 | 2009–2014 |
| Milton, VT, US | 6 | 2005–2009 |
| Cheshire, GB | 1 | 2014 |