Inventor
Ashish Pancholy
Inventor
Milpitas, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores52%
H03KPulse technique16%
G01RMeasuring electric variables12%
B82YSpecific uses or applications of nanostructures4%
G06FElectric digital data processing4%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light4%
H10BElectronic memory devices4%
H10DInorganic electric semiconductor devices4%
PatentTitleYear
7,809,035'Eye-safe laser navigation sensor'20106,862,215'MRAM data line configuration and method of operation'20056,775,191'Memory circuit with selective address path'20046,683,815'Magnetic memory cell and method for assigning tunable writing currents'20046,664,810'Multi-level programmable voltage control and output buffer with selectable operating voltage'20036,639,831'Localized MRAM data line and method of operation'20036,445,645'Random access memory having independent read port and write port and process for writing to and reading from the same'20026,388,927'Direct bit line-bit line defect detection test mode for SRAM'20026,385,128'Random access memory having a read/write address bus and process for writing to and reading from the same'20026,380,762'Multi-level programmable voltage control and output buffer with selectable operating voltage'20026,359,316'Method and apparatus to prevent latch-up in CMOS devices'20026,292,403'Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method'20016,286,118'Scan path circuitry including a programmable delay circuit'20016,262,937'Synchronous random access memory having a read/write address bus and process for writing to and reading from the same'20016,262,936'Random access memory having independent read port and write port and process for writing to and reading from the same'20016,115,836'Scan path circuitry for programming a variable clock pulse width'20006,069,839'Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method'20006,006,347'Test mode features for synchronous pipelined memories'19995,953,285'Scan path circuitry including an output register having a flow through mode'19995,936,977'Scan path circuitry including a programmable delay circuit'19995,903,174'Method and apparatus for reducing skew among input signals within an integrated circuit'19995,864,251'Method and apparatus for self-resetting logic circuitry'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2010Patents assigned to CYPRESS SEMICONDUCTOR CORP (18)· patent assignee history
1999–2010Based in Milpitas, CA, US· patent location history
1999–2003Based in Santa Clara, CA, US· patent location history
1999Based in Milipitas, CA, US· patent location history
2003–2005Patents assigned to SILICON MAGNETIC SYSTEMS (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CYPRESS SEMICONDUCTOR CORP | 18 | 1999–2010 |
| SILICON MAGNETIC SYSTEMS | 4 | 2003–2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Milpitas, California, US | 17 | 1999–2010 |
| Santa Clara, California, US | 4 | 1999–2003 |
| Milipitas, California, US | 1 | 1999 |