Inventor

Kelly W. Kyler

Inventor
Mesa, AZ, US

Overview

22→
Patents
1996–2010
Patent span
Electricity
Primary field (CPC H)

Patents· 22 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores22%
H10BElectronic memory devices22%
B82YSpecific uses or applications of nanostructures17%
H10NElectric solid-state devices not otherwise provided for17%
H10DInorganic electric semiconductor devices4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y10TTechnical subjects covered by former us classification4%
H01FMagnets3%
H05KPrinted circuits1%
PatentTitleYear
7,833,806'Structure and method for fabricating cladded conductive lines in magnetic memories'20107,476,329'Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices'20097,402,529'Method of applying cladding material on conductive lines of MRAM devices'20087,105,903'Methods and structures for electrical communication with an overlying electrode for a semiconductor element'20067,105,363'Cladded conductor for use in a magnetoelectronics device and method for fabricating the same'20066,936,763'Magnetic shielding for electronic circuits which include magnetic materials'20056,927,072'Method of applying cladding material on conductive lines of MRAM devices'20056,912,107'Magnetic element with insulating veils and fabricating method thereof'20056,911,156'Methods for fabricating MRAM device structures'20056,885,074'Cladded conductor for use in a magnetoelectronics device and method for fabricating the same'20056,881,351'Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices'20056,835,423'Method of fabricating a magnetic element with insulating veils'20046,812,040'Method of fabricating a self-aligned via contact for a magnetic memory element'20046,783,994'Method of fabricating a self-aligned magnetic tunneling junction and via contact'20046,518,071'Magnetoresistive random access memory device and method of fabrication thereof'20036,365,419'High density MRAM cell array'20026,334,929'Plasma processing method'20026,211,090'Method of fabricating flux concentrating layer for use with magnetoresistive random access memories'20016,174,737'Magnetic random access memory and fabricating method thereof'20016,153,443'Method of fabricating a magnetic random access memory'20005,940,319'Magnetic random access memory and fabricating method thereof'19995,512,518'Method of manufacture of multilayer dielectric on a III-V substrate'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2003Patents assigned to MOTOROLA INC (8)· patent assignee history
1996–2002Based in Chandler, AZ, US· patent location history
1999–2010Based in Mesa, AZ, US· patent location history
2004–2008Patents assigned to FREESCALE SEMICONDUCTOR INC (12)· patent assignee history
2009–2010Patents assigned to EVERSPIN TECHNOLOGIES INC (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FREESCALE SEMICONDUCTOR INC122004–2008
MOTOROLA INC81996–2003
EVERSPIN TECHNOLOGIES INC22009–2010
Locations
LocationPatentsSpan
Mesa, AZ, US201999–2010
Chandler, AZ, US21996–2002