Inventor
Frank Worrell
Inventor
San Jose, CA, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing83%
H04LTransmission of digital information, e.g. telegraphic communication10%
H03KPulse technique3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
PatentTitleYear
9,928,193'Distributed timer subsystem'20189,667,446'Condition code approach for comparing rule and packet data that are provided in portions'20179,568,944'Distributed timer subsystem across multiple devices'20179,544,402'Multi-rule approach to encoding a group of rules'20178,046,505'Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features'20117,966,431'Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features'20117,797,467'Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features'20107,681,017'Pseudo pipeline and pseudo pipelined SDRAM controller'20107,069,363'On-chip bus'20066,973,561'Processor pipeline stall based on data register status'20056,948,054'Simple branch prediction and misprediction recovery method'20056,877,082'Central processing unit including address generation system and instruction fetch apparatus'20056,728,816'Simple mechanism for guaranteeing in order read data return on a split transaction bus'20046,671,781'Data cache store buffer'20036,584,537'Data-cache data-path'20036,412,066'Microprocessor employing branch instruction to set compression mode'20026,012,138'Dynamically variable length CPU pipeline for efficiently executing two instruction sets'20005,982,194'Arithmetic and logic function circuits optimized for datapath layout'19995,931,941'Interface for a modularized computational unit to a CPU'19995,905,893'Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set'19995,896,519'Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions'19995,867,681'Microprocessor having register dependent immediate decompression'19995,794,010'Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor'19985,784,634'Pipelined CPU with instruction fetch, execution and write back stages'19985,774,709'Enhanced branch delay slot handling with single exception program counter'19985,729,482'Microprocessor shifter using rotation and masking operations'19985,670,900'Mask decoder circuit optimized for data path'19975,648,733'Scan compatible 3-state bus control'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2006Patents assigned to LSI LOGIC CORP (20)· patent assignee history
1997–2018Based in San Jose, CA, US· patent location history
2010–2011Patents assigned to LSI CORP (4)· patent assignee history
2017–2018Patents assigned to CAVIUM INC (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 20 | 1997–2006 |
| CAVIUM INC | 4 | 2017–2018 |
| LSI CORP | 4 | 2010–2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 28 | 1997–2018 |