Inventor
Gary Paul McClannahan
Inventor
Rochester, MN, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing63%
H04LTransmission of digital information, e.g. telegraphic communication16%
G11CStatic stores5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses5%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
PatentTitleYear
8,879,570'Systems and methods for reconfiguring a network adapter in sleep mode'20147,430,725'Suite of tools to design integrated circuits'20087,157,948'Method and apparatus for calibrating a delay line'20077,149,218'Cache line cut through of limited life data in a data processing system'20067,055,113'Simplified process to design integrated circuits'20067,043,611'Reconfigurable memory controller'20066,765,911'Communications adapter for implementing communications in a network and providing multiple modes of communications'20046,601,122'Exceptions and interrupts with dynamic priority and vector routing'20036,536,014'Reusable configuration tool'20036,498,782'Communications methods and gigabit ethernet communications adapter providing quality of service and receiver connection speed differentiation'20026,453,366'Method and apparatus for direct memory access (DMA) with dataflow blocking for users'20026,453,434'Dynamically-tunable memory controller'20026,438,670'Memory controller with programmable delay counter for tuning performance based on timing parameter of controlled memory storage device'20026,334,174'Dynamically-tunable memory controller'20016,289,430'Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags'20015,471,626'Variable stage entry/exit instruction pipeline'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2006Patents assigned to IBM (11)· patent assignee history
1995–2014Based in Rochester, MN, US· patent location history
2006–2007Patents assigned to LSI LOGIC CORP (3)· patent assignee history
2014Patents assigned to BANSAL YASH (1)· patent assignee history
2014Patents assigned to BRANSTAD MARK (1)· patent assignee history
2014Patents assigned to BROCADE COMM SYSTEMS INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 11 | 1995–2006 |
| LSI LOGIC CORP | 3 | 2006–2007 |
| BANSAL YASH | 1 | 2014 |
| BRANSTAD MARK | 1 | 2014 |
| BROCADE COMM SYSTEMS INC | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Rochester, Minnesota, US | 16 | 1995–2014 |