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Inventor

James A. Gasbarro

Inventor
Mountain View, CA, US

Overview

44→
Patents
1993–2020
Patent span
Physics
Primary field (CPC G)

Patents· 44 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores34%
G06FElectric digital data processing16%
H04LTransmission of digital information, e.g. telegraphic communication7%
A61BDiagnosis6%
G01RMeasuring electric variables6%
H03KPulse technique6%
A61HPhysical therapy apparatus, e.g. devices for locating or stimulating reflex points in the body4%
H04BTransmission4%
G01KMeasuring temperature3%
G16HHealthcare informatics, i.e. information and communication technology [ict] specially adapted for the handling or processing of medical or healthcare data3%
PatentTitleYear
10,784,928Rotary data coupler202010,498,403Rotary data coupler201910,177,820Rotary data coupler20199,204,806'Apparatus using temperature data to make predictions about an individual'20159,114,053'Pneumatic compression therapy system and methods of using same'20158,663,106'Non-invasive temperature monitoring device'20148,369,936'Wearable apparatus for measuring heart-related parameters and deriving human status parameters from sensed physiological and contextual parameters'20138,344,998'Gesture-based power management of a wearable portable electronic device with display'20138,202,236'Methods for enhancing pressure accuracy in a compression pump'20128,205,056'Memory controller for controlling write signaling'20128,182,437'Pneumatic compression therapy system and methods of using same'20127,793,039'Interface for a semiconductor memory device and method for controlling the interface'20107,536,494'Expandable slave device system with buffered subsystems'20097,502,643'Method and apparatus for measuring heart related parameters'20097,496,709'Integrated circuit memory device having delayed write timing based on read response time'20097,360,050'Integrated circuit memory device having delayed write capability'20087,330,952'Integrated circuit memory device having delayed write timing based on read response time'20087,330,953'Memory system having delayed write timing'20087,287,119'Integrated circuit memory device with delayed write command processing'20077,222,209'Expandable slave device system'20077,199,605'Method and apparatus for low capacitance, high output impedance driver'20077,197,611'Integrated circuit memory device having write latency function'2007RE039153'Connector with integral transmission line bus'20067,002,367'Method and apparatus for low capacitance, high output impedance driver'20066,868,474'High performance cost optimized memory'20056,687,780'Expandable slave device system'20046,671,836'Method and apparatus for testing memory'20036,509,756'Method and apparatus for low capacitance, high output impedance driver'20036,401,167'High performance cost optimized memory'20026,330,193'Method and apparatus for low capacitance, high output impedance driver'20016,308,232'Electronically moveable terminator and method for using same in a memory system'20016,266,730'High-frequency bus system'20016,075,730'High performance cost optimized memory with delayed memory writes'20006,067,594'High frequency bus system'20006,009,487'Method and apparatus for setting a current of an output driver for the high speed bus'19995,908,333'Connector with integral transmission line bus'19995,844,913'Current mode interface circuitry for an IC test device'19985,446,696'Method and apparatus for implementing refresh in a synchronous DRAM system'19955,432,823'Method and circuitry for minimizing clock-data skew in a bus system'19955,357,195'Testing set up and hold input timing parameters of high speed integrated circuit devices'19945,337,285'Method and apparatus for power control in devices'19945,325,053'Apparatus for testing timing parameters of high speed integrated circuit devices'19945,268,639'Testing timing parameters of high speed integrated circuit devices'19935,254,883'Electrical current source circuitry for a bus'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2012Patents assigned to RAMBUS INC (33)· patent assignee history
1993–2012Based in Mountain View, CA, US· patent location history
2001–2020Based in Pittsburgh, PA, US· patent location history
2004–2015Based in Fox Chapel, PA, US· patent location history
2009–2015Patents assigned to BODYMEDIA INC (4)· patent assignee history
2012–2015Patents assigned to GASBARRO JAMES (6)· patent assignee history
2013–2015Patents assigned to ANDRE DAVID (3)· patent assignee history
2013–2015Patents assigned to BOEHMKE SCOTT (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
RAMBUS INC331993–2012
GASBARRO JAMESself62012–2015
BODYMEDIA INC42009–2015
ANDRE DAVID32013–2015
BOEHMKE SCOTT32013–2015
Locations
LocationPatentsSpan
Mountain View, California, US251993–2012
Pittsburgh, Pennsylvania, US132001–2020
Fox Chapel, Pennsylvania, US62004–2015