LexDanaLexDanabeta
Inventor

Neil McLellan

Inventor
Danville, CA, US

Overview

78→
Patents
1988–2018
Patent span
Electricity
Primary field (CPC H)

Patents· 78 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1046%
H05KPrinted circuits13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H01LSemiconductor devices6%
Y10TTechnical subjects covered by former us classification6%
B23KSoldering or unsoldering2%
G04GElectronic time-pieces2%
H01RElectrically-conductive connections2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
H01MProcesses or means, e.g. batteries, for the direct conversion of chemical energy into electrical energy1%
PatentTitleYear
9,867,282'Circuit board with corner hollows'20189,793,199'Circuit board with via trace connection and method of making the same'20179,607,935'Semiconductor chip package with undermount passive devices'20179,520,306'Method of fabricating an integrated circuit (IC) package having a plurality of spaced apart pad portion'20169,449,903'Ball grid array package with improved thermal characteristics'20169,318,457'Methods of fabricating semiconductor chip solder structures'20169,142,520'Methods of fabricating semiconductor chip solder structures'20158,847,383'Integrated circuit package strip with stiffener'20148,785,317'Wafer level packaging of semiconductor chips'20148,704,353'Thermal management of stacked semiconductor chips with electrically non-functional interconnects'20148,647,974'Method of fabricating a semiconductor chip with supportive terminal pad'20148,633,599'Semiconductor chip with underfill anchors'20148,610,262'Ball grid array package with improved thermal characteristics'20138,564,122'Circuit board component shim structure'20138,445,329'Circuit board with oval micro via'20138,389,340'Methods of forming semiconductor chip underfill anchors'20138,344,505'Wafer level packaging of semiconductor chips'20138,330,270'Integrated circuit package having a plurality of spaced apart pad portions'20128,314,474'Under bump metallization for on-die capacitor'20128,294,266'Conductor bump method and apparatus'20128,120,170'Integrated package circuit with stiffener'20128,058,108'Methods of forming semiconductor chip underfill anchors'20117,994,044'Semiconductor chip with contoured solder structure opening'20117,985,621'Method and apparatus for making semiconductor packages'20117,969,020'Die stacking apparatus and method'20117,906,424'Conductor bump method and apparatus'20117,799,608'Die stacking apparatus and method'20107,732,914'Cavity-type integrated circuit package'20107,595,225'Leadless plastic chip carrier with contact standoff'20097,411,289'Integrated circuit package with partially exposed contact pads and process for fabricating the same'20087,371,610'Process for fabricating an integrated circuit package with reduced mold warping'20087,372,151'Ball grid array package and process for manufacturing same'20087,358,119'Thin array plastic package without die attach pad and process for fabricating the same'20087,342,305'Thermally enhanced cavity-down integrated circuit package'20087,315,080'Ball grid array package that includes a collapsible spacer for separating die adapter from a heat spreader'20087,270,867'Leadless plastic chip carrier'20077,271,032'Leadless plastic chip carrier with etch back pad singulation'20077,247,526'Process for fabricating an integrated circuit package'20077,232,755'Process for fabricating pad frame and integrated circuit package'20077,226,811'Process for fabricating a leadless plastic chip carrier'20077,224,048'Flip chip ball grid array package'20077,091,581'Integrated circuit package and process for fabricating the same'20066,995,460'Leadless plastic chip carrier with etch back pad singulation'20066,989,294'Leadless plastic chip carrier with etch back pad singulation'20066,987,032'Ball grid array package and process for manufacturing same'20066,984,785'Thermally enhanced cavity-down integrated circuit package'20066,946,324'Process for fabricating a leadless plastic chip carrier'20056,940,154'Integrated circuit package and method of manufacturing the integrated circuit package'20056,933,176'Ball grid array package and process for manufacturing same'20056,933,594'Leadless plastic chip carrier with etch back pad singulation'20056,903,304'Process for dressing molded array package saw blade'20056,872,661'Leadless plastic chip carrier with etch back pad singulation and die attach pad array'20056,841,859'Premolded cavity IC package'20056,821,817'Premolded cavity IC package'20046,790,710'Method of manufacturing an integrated circuit package'20046,737,755'Ball grid array package with improved thermal characteristics'20046,667,191'Chip scale integrated circuit package'20036,635,957'Leadless plastic chip carrier with etch back pad singulation and die attach pad array'20036,585,905'Leadless plastic chip carrier with partial etch die attach pad'20036,498,099'Leadless plastic chip carrier with etch back pad singulation'20026,429,048'Metal foil laminated IC package'20026,294,100'Exposed die leadless plastic chip carrier'20016,242,281'Saw-singulated leadless plastic chip carrier'20016,229,200'Saw-singulated leadless plastic chip carrier'20016,021,046'Thermal protection of electrical elements systems'20006,020,634'Replaceable power module'20005,913,552'Method of providing thermal protection of electrical elements'19995,892,304'Power cap'19995,821,619'Replaceable power module'19985,682,068'Power cap'1997D0384336'Power cap cover'19975,647,121'Method of assembling electronic component'19975,579,206'Enhanced low profile sockets and module systems'19965,528,463'Low profile sockets and modules for surface mountable applications'19965,130,783'Flexible film semiconductor package'19924,921,550'Delayed reflow alloy mix solder paste'19904,865,654'Delayed reflow alloy mix solder paste'19894,767,471'Delayed reflow alloy mix solder paste'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2000Based in Garland, TX, US· patent location history
1996–2000Patents assigned to DALLAS SEMICONDUCTOR (10)· patent assignee history
2001–2008Patents assigned to ASAT LTD (35)· patent assignee history
2001–2007Based in Hong Kong, CN· patent location history
2005–2016Based in Danville, CA, US· patent location history
2009–2018Patents assigned to MCLELLAN NEIL (19)· patent assignee history
2010–2018Patents assigned to ADVANCED MICRO DEVICES INC (11)· patent assignee history
2010–2017Based in Toronto, CA· patent location history
2011–2018Patents assigned to ATI TECHNOLOGIES ULC (18)· patent assignee history
2012–2018Based in Austin, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ASAT LTD352001–2008
MCLELLAN NEILself192009–2018
ATI TECHNOLOGIES ULC182011–2018
ADVANCED MICRO DEVICES INC112010–2018
DALLAS SEMICONDUCTOR101996–2000
Locations
LocationPatentsSpan
Danville, California, US222005–2016
Toronto, CA162010–2017
Garland, Texas, US111992–2000
Hong Kong, CN82001–2007
Austin, Texas, US72012–2018