Inventor
Richard H. Livengood
Inventor
Los Gatos, CA, US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1041%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
B24BMachines, devices, or processes for grinding or polishing11%
H01JElectric discharge tubes or discharge lamps6%
H10DInorganic electric semiconductor devices6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G01QScanning-probe techniques or apparatus2%
G01RMeasuring electric variables2%
G06FElectric digital data processing2%
H03KPulse technique2%
PatentTitleYear
7,232,526'Method and apparatus for controlling material removal from semiconductor substrate using induced current endpointing'20077,205,566'Transistor-level signal cutting method and structure'20077,183,122'Physical nano-machining with a scanning probe system for integrated circuit modification'20077,141,439'Transistor-level signal cutting method and structure'20066,855,946'Fiducial transistor in an integrated circuit'20056,825,557'Localized backside chip cooling with integrated smart valves'20046,780,658'Method and apparatus for controlling material removal from a semiconductor substrate using induced current endpointing'20046,753,541'Method and apparatus for making and using a beacon fiducial for an integrated circuit'20046,579,732'Method and apparatus for controlling material removal from a semiconductor substrate using induced current endpointing'20036,528,895'Method and apparatus for making and using an improved fiducial for an integrated circuit'20036,525,922'High performance via capacitor and method for manufacturing same'20036,495,454'Substrate interconnect for power distribution on integrated circuits'20026,448,168'Method for distributing a clock on the silicon backside of an integrated circuit'20026,373,572'Method and apparatus for making and using an improved fiducial for an intergrated circuit'20026,355,494'Method and apparatus for controlling material removal from a semiconductor substrate using induced current endpointing'20026,355,950'Substrate interconnect for power distribution on integrated circuits'20026,316,981'Signal distribution network on backside of substrate'20016,309,897'Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die'20016,222,246'Flip-chip having an on-chip decoupling capacitor'20016,159,753'Method and apparatus for editing an integrated circuit'20006,153,891'Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die'20006,150,718'Method and apparatus for performing a circuit edit through the back side of an integrated circuit die'20006,122,174'Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate'20006,037,822'Method and apparatus for distributing a clock on the silicon backside of an integrated circuit'20006,020,746'Method and apparatus for probing an integrated circuit through the back side of an integrated circuit die'20006,001,703'Method of forming a fiducial for aligning an integrated circuit die'19995,976,980'Method and apparatus providing a mechanical probe structure in an integrated circuit die'19995,952,247'Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate'19995,948,217'Method and apparatus for endpointing while milling an integrated circuit'19995,942,805'Fiducial for aligning an integrated circuit die'19995,904,486'Method for performing a circuit edit through the back side of an integrated circuit die'19995,805,421'Semiconductor substrate having alignment marks for locating circuitry on the substrate'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2007Patents assigned to INTEL CORP (32)· patent assignee history
1998–2000Based in Fremont, CA, US· patent location history
1999–2005Based in Los Gatos, CA, US· patent location history
2002–2007Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 32 | 1998–2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Gatos, California, US | 20 | 1999–2005 |
| San Jose, California, US | 9 | 2002–2007 |
| Fremont, California, US | 3 | 1998–2000 |