Inventor

Bruce Whitefield

Inventor
Camas, WA, US

Overview

32→
Patents
1995–2014
Patent span
Physics
Primary field (CPC G)

Patents· 32 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
G06FElectric digital data processing12%
G01RMeasuring electric variables10%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices10%
G05BControl or regulating systems in general10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y02PClimate change mitigation technologies in the production or processing of goods8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
B24BMachines, devices, or processes for grinding or polishing2%
B62BHand-propelled vehicles, e.g. hand carts or perambulators2%
PatentTitleYear
8,899,599'Clamping mechanism for a two wheel panel dolly'20147,930,655'Yield profile manipulator'20117,799,166'Wafer edge expose alignment method'20107,653,523'Method for calculating high-resolution wafer parameter profiles'20107,598,127'Nanotube fuse structure'20097,560,292'Voltage contrast monitor for integrated circuit defects'20097,460,211'Apparatus for wafer patterning to reduce edge exclusion zone'20087,395,522'Yield profile manipulator'20087,323,768'Voltage contrast monitor for integrated circuit defects'20087,315,360'Surface coordinate system'20087,312,880'Wafer edge structure measurement method'20077,277,813'Pattern detection for integrated circuit substrates'20077,183,181'Dynamic edge bead removal'20077,137,098'Pattern component analysis and manipulation'20067,074,710'Method of wafer patterning for reducing edge exclusion zone'20067,062,415'Parametric outlier detection'20067,039,556'Substrate profile analysis'20067,013,192'Substrate contact analysis'20066,986,112'Method of mapping logic failures in an integrated circuit die'20066,971,944'Method and control system for improving CMP process by detecting and reacting to harmonic oscillation'20056,943,042'Method of detecting spatially correlated variations in a parameter of an integrated circuit die'20056,936,920'Voltage contrast monitor for integrated circuit defects'20056,787,379'Method of detecting spatially correlated variations in a parameter of an integrated circuit die'20046,767,692'Process for inhibiting edge peeling of coating on semiconductor substrate during formation of integrated circuit structure thereon'20046,650,958'Integrated process tool monitoring system for semiconductor fabrication'20036,645,857'Key hole filling'20036,614,507'Apparatus for removing photoresist edge beads from thin film substrates'20036,512,985'Process control system'20036,495,312'Method and apparatus for removing photoresist edge beads from thin film substrates'20025,654,897'Method and structure for improving patterning design for processing'19975,477,466'Method and structure for improving patterning design for processing'19955,379,233'Method and structure for improving patterning design for processing'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2009Patents assigned to LSI LOGIC CORP (23)· patent assignee history
1995–1997Based in Menlo Park, CA, US· patent location history
2002–2014Based in Camas, WA, US· patent location history
2007–2011Patents assigned to LSI CORP (7)· patent assignee history
2009Patents assigned to NANTERO INC (1)· patent assignee history
2014Patents assigned to WHITEFIELD BRUCE JOSEPH (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LSI LOGIC CORP231995–2009
LSI CORP72007–2011
NANTERO INC12009
WHITEFIELD BRUCE JOSEPHself12014
Locations
LocationPatentsSpan
Camas, Washington, US292002–2014
Menlo Park, California, US31995–1997