Inventor
Ravi Kiran Nalla
Inventor
San Jose, CA, US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H05KPrinted circuits18%
G02BOptical elements, systems or apparatus9%
H04NPictorial communication, e.g. television9%
H01LSemiconductor devices6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
F21VFunctional features or details of lighting devices or systems thereof3%
G06TImage data processing or generation, in general3%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light3%
B23KSoldering or unsoldering2%
PatentTitleYear
10,652,475Structured light 3D sensors with variable focal length lenses and illuminators202010,602,039Ultra-compact image sensor assembly for thin profile devices202010,521,6503D imaging recognition by stereo matching of RGB and infrared images201910,469,758Structured light 3D sensors with variable focal length lenses and illuminators201910,430,647Tailored illumination profile for articulated hand tracking201910,386,486Systems and methods for time of flight laser pulse engineering201910,372,9743D imaging recognition by stereo matching of RGB and infrared images201910,261,328Enhanced illumination system201910,257,932Laser diode chip on printed circuit board201910,154,197Image capture device having light field image capture mode, 2D image capture mode, and intermediate capture mode201810,051,723High thermal conductivity region for optoelectronic devices201810,048,498Illumination module201810,003,726Illumination module for near eye-to-eye display system20189,929,097'Mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers'20189,851,478Optical cross talk mitigation for optical device having disrupting features formed on a shield20179,780,054'Semiconductor package with embedded die and its methods of fabrication'20179,769,398'Image sensor with large-area global shutter contact'20179,726,962'Enhanced camera module mount'20179,411,122'Light field image capture device having 2D image capture mode'20169,406,618'Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same'20169,257,380'Forming functionalized carrier structures with coreless packages'20169,214,439'Forming in-situ micro-feature structures with coreless packages'20159,077,901'Light field image capture device having 2D image capture mode'20159,040,842'Mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers'20158,901,724'Semiconductor package with embedded die and its methods of fabrication'20148,896,116'Microelectronic package and method of manufacturing same'20148,809,124'Bumpless build-up layer and laminated core hybrid structures and methods of assembling same'20148,786,066'Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same'20148,772,924'Forming in-situ micro-feature structures with coreless packages'20148,618,652'Forming functionalized carrier structures with coreless packages'20138,580,616'Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby'20138,507,324'Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages'20138,508,037'Bumpless build-up layer and laminated core hybrid structures and methods of assembling same'20138,431,438'Forming in-situ micro-feature structures with coreless packages'20138,425,785'Mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers'20138,319,318'Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages'20128,304,913'Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby'20128,252,677'Method of forming solder bumps on substrates'20128,183,692'Barrier layer for fine-pitch mask-based substrate bumping'20127,985,622'Method of forming collapse chip connection bumps on a semiconductor substrate'20117,831,115'Optical die structures and associated package substrates'20107,825,022'Method of enabling solder deposition on a substrate and electronic package formed thereby'20107,776,734'Barrier layer for fine-pitch mask-based substrate bumping'20107,651,021'Microball attachment using self-assembly for substrate bumping'20107,583,871'Substrates for optical die structures'20097,538,429'Method of enabling solder deposition on a substrate and electronic package formed thereby'20097,494,913'Microball placement solutions'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2018Patents assigned to INTEL CORP (28)· patent assignee history
2009–2018Patents assigned to NALLA RAVI (5)· patent assignee history
2009–2014Based in Chandler, AZ, US· patent location history
2012–2014Patents assigned to NALLA RAVI K (11)· patent assignee history
2012–2014Patents assigned to MANUSHAROW MATHEW J (5)· patent assignee history
2013–2020Based in San Jose, CA, US· patent location history
2017–2020Patents assigned to MICROSOFT TECHNOLOGY LICENSING LLC (15)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 28 | 2009–2018 |
| MICROSOFT TECHNOLOGY LICENSING LLC | 15 | 2017–2020 |
| NALLA RAVI Kself | 11 | 2012–2014 |
| MANUSHAROW MATHEW J | 5 | 2012–2014 |
| NALLA RAVIself | 5 | 2009–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 30 | 2013–2020 |
| Chandler, AZ, US | 17 | 2009–2014 |