Inventor
Michael J. Nystrom
Inventor
San Jose, CA, US
Overview
Patents· 36 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G02Bprimary
G02BOptical elements, systems or apparatus15%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H01JElectric discharge tubes or discharge lamps10%
Y10TTechnical subjects covered by former us classification10%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems7%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein6%
B81BMicrostructural devices or systems, e.g. micromechanical devices4%
G01RMeasuring electric variables4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%
B23KSoldering or unsoldering3%
PatentTitleYear
11,125,969Bonding of resonant oscillating mirror to frame202111,016,289Micromirror actuator assembly202110,962,766Adhesive bonded micro electro mechanical system202110,895,713Actuator frame for scanning mirror202110,890,755Steerable optical assemblies202110,712,550Colocating signal processing device with micromechanical scanning silicon mirror20209,874,774Method and apparatus for testing operation of an optical liquid crystal device20189,548,145'Microelectronic assembly with multi-layer support structure'20179,239,479'Calibration of tunable liquid crystal optical device'20169,140,920'Method and apparatus for testing operation of an optical liquid crystal device'20158,604,605'Microelectronic assembly with multi-layer support structure'20138,558,985'Contact structure for a tunable liquid crystal optical device'20137,936,062'Wafer level chip packaging'20117,858,445'Wire bonded wafer level cavity package'20107,737,513'Chip assembly including package element and integrated circuit chip'20107,593,636'Pin referenced image sensor to reduce tilt in a camera module'20097,569,424'Method of forming a wall structure in a microelectronic assembly'20097,521,276'Compliant terminal mountings with vented spaces and methods'20097,453,139'Compliant terminal mountings with vented spaces and methods'20087,449,779'Wire bonded wafer level cavity package'20087,315,115'Light-emitting and electron-emitting devices having getter regions'20087,206,474'Heating of trenches in an optical bubble switch'20077,196,536'Method and apparatus for non-contact electrical probe'20077,094,304'Method for selective area stamping of optical elements on a substrate'20067,090,554'Fabrication of flat-panel display having spacer with rough face for inhibiting secondary electron escape'20066,958,446'Compliant and hermetic solder seal'20056,861,798'Tailored spacer wall coatings for reduced secondary electron emission'20056,732,905'Vented cavity, hermetic solder seal'20046,734,608'Constitution and fabrication of flat-panel display and porous-faced structure suitable for partial of full use in spacer of flat-panel display'20046,691,404'Fabricating of a flat-panel displace using porous spacer'20046,617,772'Flat-panel display having spacer with rough face for inhibiting secondary electron escape'20036,560,383'High efficiency insulation for improving thermal efficiency of bubble optical switch'20036,477,222'Getter for atmospheric gases in optical switch working fluid'20026,403,209'Constitution and fabrication of flat-panel display and porous-faced structure suitable for partial or full use in spacer of flat-panel display'20026,208,453'Oriented niobate ferroelectric thin films for electrical and optical devices'20015,753,300'Oriented niobate ferroelectric thin films for electrical and optical devices and method of making such films'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998Based in Germantown, MD, US· patent location history
2001Based in Chicago, IL, US· patent location history
2002–2007Patents assigned to AGILENT TECHNOLOGIES INC (6)· patent assignee history
2002–2005Patents assigned to CANDESCENT INTELLECTUAL PROP (5)· patent assignee history
2002–2005Patents assigned to CANDESCENT TECH CORP (5)· patent assignee history
2002–2018Based in San Jose, CA, US· patent location history
2008–2010Patents assigned to TESSERA INC (7)· patent assignee history
2020–2021Patents assigned to MICROSOFT TECHNOLOGY LICENSING LLC (6)· patent assignee history
2020–2021Based in Mercer Island, WA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TESSERA INC | 7 | 2008–2010 |
| AGILENT TECHNOLOGIES INC | 6 | 2002–2007 |
| MICROSOFT TECHNOLOGY LICENSING LLC | 6 | 2020–2021 |
| CANDESCENT INTELLECTUAL PROP | 5 | 2002–2005 |
| CANDESCENT TECH CORP | 5 | 2002–2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 28 | 2002–2018 |
| Mercer Island, Washington, US | 6 | 2020–2021 |
| Chicago, Illinois, US | 1 | 2001 |
| Germantown, Maryland, US | 1 | 1998 |