Inventor
Henley Liu
Inventor
San Jose, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices26%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10DInorganic electric semiconductor devices6%
G01RMeasuring electric variables4%
H10KOrganic electric solid-state devices4%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein2%
G06FElectric digital data processing2%
G09FDisplaying2%
G09GArrangements or circuits for control of indicating devices using static means to present variable information2%
PatentTitleYear
11,003,035Display panel and display device202110,992,277Variable gain amplifier with embedded equalization for uniform tuning202110,972,108Systems and methods for reduction of in-phase and quadrature-phase (IQ) clock skew202110,916,738Display panel and manufacturing method of the display panel, display device202110,886,341Display panel and method for preparing the same, display panel motherboard and display device202110,770,430Package integration for memory devices202010,720,377Electronic device apparatus with multiple thermally conductive paths for heat dissipation202010,692,837Chip package assembly with modular core dice202010,629,512Integrated circuit die with in-chip heat sink202010,593,638Methods of interconnect for high density 2.5D and 3D integration202010,529,645Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management202010,527,670Testing system for lid-less integrated circuit packages202010,431,565Wafer edge partial die engineered for stacked die yield201910,319,606Chip package assembly with enhanced interconnects and method for fabricating the same201910,262,911Circuit for and method of testing bond connections between a first die and a second die20199,412,674'Shielded wire arrangement for die testing'20169,337,138'Capacitors within an interposer coupled to supply and ground planes of a substrate'20168,810,269'Method of testing a semiconductor structure'20148,802,454'Methods of manufacturing a semiconductor structure'20148,354,671'Integrated circuit with adaptive VGG setting'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2020Patents assigned to XILINX INC (15)· patent assignee history
2013–2016Patents assigned to LIU HENLEY (3)· patent assignee history
2013–2020Based in San Jose, CA, US· patent location history
2021Patents assigned to BOE TECHNOLOGY GROUP CO LTD (3)· patent assignee history
2021Patents assigned to HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO LTD (2)· patent assignee history
2021Patents assigned to QUALCOMM INC (2)· patent assignee history
2021Based in Beijing, CN· patent location history
2021Based in San Diego, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 15 | 2013–2020 |
| BOE TECHNOLOGY GROUP CO LTD | 3 | 2021 |
| LIU HENLEYself | 3 | 2013–2016 |
| HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO LTD | 2 | 2021 |
| QUALCOMM INC | 2 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 15 | 2013–2020 |
| Beijing, CN | 3 | 2021 |
| San Diego, California, US | 2 | 2021 |