Inventor
ASHISH AGRAWAL
Inventor
US
Overview
Patents· 55 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices26%
H01LSemiconductor devices23%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
B82YSpecific uses or applications of nanostructures6%
G06FElectric digital data processing4%
H04LTransmission of digital information, e.g. telegraphic communication4%
F01DNon-positive displacement machines or engines, e.g. steam turbines3%
F05DIndexing scheme for aspects relating to non-positive-displacement machines or engines, gas-turbines or jet-propulsion plants3%
G06NComputing arrangements based on specific computational models2%
PatentTitleYear
12,581,717Frontside and backside epi contact202612,557,340Cladding and condensation for strained semiconductor nanoribbons202612,557,352Forksheet transistor device with air gap spine202612,543,351Enriched semiconductor nanoribbons for producing intrinsic compressive strain202612,538,516Forksheet transistor with asymmetric dielectric spine202612,414,339Formation of gate spacers for strained PMOS gate-all-around transistor structures202512,388,011Top gate recessed channel CMOS thin film transistor and methods of fabrication202512,320,268Turbine exhaust collector202512,301,904User interface customization in a television platform202512,266,570Self-aligned interconnect structures and methods of fabrication202512,255,234Integrated circuit structures having germanium-based channels202512,211,794Integrated circuits and methods for forming thin film crystal layers202512,199,142Neighboring gate-all-around integrated circuit structures having conductive contact stressor between epitaxial source or drain regions202512,120,865Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure202411,996,404Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material202411,983,522Edge-based intelligence for over the air update202411,973,143Source or drain structures for germanium N-channel devices202411,929,320Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication202411,923,421Integrated circuit structures having germanium-based channels202411,907,706System and method of analyzing update readiness for distributed software systems202411,887,988Thin film transistor structures with regrown source and drain202411,873,728Exhaust collector conversion system and method202411,862,715Vertical tunneling field-effect transistors202411,830,788Integrated circuits and methods for forming integrated circuits202311,803,816Workflow service email integration202311,743,356Email notification system202311,721,766Metal-assisted single crystal transistors202311,683,246Edge-based intelligence for anomaly detection202311,670,588Selectable vias for back end of line interconnects202311,645,158Automated rollback in virtualized computing environments202311,626,519Fabrication of non-planar IGZO devices for improved electrostatics202311,598,224Exhaust collector conversion system and method202311,575,005Asymmetrical semiconductor nanowire field-effect transistor202311,482,622Adhesion structure for thin film transistor202211,476,164Integrated circuit structures having differentiated workfunction layers202211,473,450Turbine exhaust collector202211,462,568Stacked thin film transistors202211,450,527Engineering tensile strain buffer in art for high quality Ge channel202211,450,739Germanium-rich nanowire transistor with relaxed buffer layer202211,437,472Integrated circuit structures having germanium-based channels202211,425,075Integration of client applications with hosted applications202211,416,909Electronic marketplace recommendations202211,404,562Tunneling field effect transistors202211,335,793Vertical tunneling field-effect transistors202211,328,988Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication202211,322,620Metal-assisted single crystal transistors202211,276,644Integrated circuits and methods for forming thin film crystal layers202211,257,042Workflow service email integration202211,256,609Systems and methods to optimize testing using machine learning202211,244,943Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material202211,233,148Reducing band-to-band tunneling in semiconductor devices202211,195,924Broken bandgap contact202111,164,785Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material202111,164,809Integrated circuits and methods for forming integrated circuits202111,152,290Wide bandgap group IV subfin to reduce leakage2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (40)· patent assignee history
2021–2026Based in US· patent location history
2022–2024Patents assigned to VMWARE INC (6)· patent assignee history
2022–2025Patents assigned to GEN ELECTRIC (4)· patent assignee history
2022–2024Based in IN· patent location history
2023–2024Patents assigned to AYLA NETWORKS INC (2)· patent assignee history
2024–2025Patents assigned to GE INFRASTRUCTURE TECHNOLOGY LLC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 40 | 2021–2026 |
| VMWARE INC | 6 | 2022–2024 |
| GEN ELECTRIC | 4 | 2022–2025 |
| AYLA NETWORKS INC | 2 | 2023–2024 |
| GE INFRASTRUCTURE TECHNOLOGY LLC | 2 | 2024–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 48 | 2021–2026 |
| IN | 7 | 2022–2024 |