Inventor
Bernard Gorowitz
Inventor
Clifton Park, NY, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
Y10TTechnical subjects covered by former us classification12%
H05KPrinted circuits10%
H10DInorganic electric semiconductor devices7%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
B05CApparatus for applying fluent materials to surfaces, in general4%
H01BCables4%
F01DNon-positive displacement machines or engines, e.g. steam turbines3%
F23NRegulating or controlling combustion3%
PatentTitleYear
6,298,551'Methods of forming compliant interface structures with partially open interiors for coupling two electrically conductive contact areas'20016,046,410'Interface structures for electronic devices'20005,973,908'Structure for thin film capacitors'19995,857,858'Demountable and repairable low pitch interconnect for stacked multichip modules'19995,757,072'Structure for protecting air bridges on semiconductor chips from damage'19985,736,448'Fabrication method for thin film capacitors'19985,699,234'Stacking of three dimensional high density interconnect modules with metal edge contacts'19975,657,537'Method for fabricating a stack of two dimensional circuit modules'19975,576,925'Flexible multilayer thin film capacitors'19965,561,085'Structure for protecting air bridges on semiconductor chips from damage'19965,527,741'Fabrication and structures of circuit modules with flexible interconnect layers'19965,524,339'Method for protecting gallium arsenide mmic air bridge structures'19965,401,687'Process for high density interconnection of substrates and integrated circuit chips containing sensitive structures'19955,391,516'Method for enhancement of semiconductor device contact pads'19955,366,906'Wafer level integration and testing'19945,303,684'Combustion control for producing low NO.sub.x emissions through use of flame spectroscopy'19945,279,706'Method and apparatus for fabricating a metal interconnection pattern for an integrated circuit module'19945,257,496'Combustion control for producing low NO.sub.x emissions through use of flame spectroscopy'19934,998,151'Power field effect devices having small cell size and low contact resistance'19914,933,742'Metallization contact system for large scale integrated circuits'19904,871,617'Ohmic contacts and interconnects to silicon and method of making same'19894,845,050'Method of making mo/tiw or w/tiw ohmic contacts to silicon'19894,824,802'Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures'19894,522,681'Method for tapered dry etching'19854,444,618'Processes and gas mixtures for the reactive ion etching of aluminum and aluminum alloys'19844,271,783'Apparatus for fluidized bed-electrostatic coating of indefinite length substrate'19814,188,413'Electrostatic-fluidized bed coating of wire'19804,100,883'Apparatus for electrostatic deposition on a running conductor'19784,074,006'Powder coatable polyester composition and electrical conductor coated therewith'1978Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1978–2001Patents assigned to GEN ELECTRIC (22)· patent assignee history
1978–2001Based in Clifton Park, NY, US· patent location history
1978–1980Based in Elnora, NY, US· patent location history
1994–1998Patents assigned to MARTIN MARIETTA CORP (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GEN ELECTRIC | 22 | 1978–2001 |
| MARTIN MARIETTA CORP | 7 | 1994–1998 |
Locations
| Location | Patents | Span |
|---|---|---|
| Clifton Park, New York, US | 27 | 1978–2001 |
| Elnora, New York, US | 2 | 1978–1980 |