Inventor
Takashi Ando
Inventor
Tuckahoe, NY, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices26%
H10DInorganic electric semiconductor devices13%
H10NElectric solid-state devices not otherwise provided for13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10BElectronic memory devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
G11CStatic stores5%
B82YSpecific uses or applications of nanostructures2%
Y10TTechnical subjects covered by former us classification2%
B22FWorking metallic powder1%
PatentTitleYear
11,011,704Forming RRAM cell structure with filament confinement202111,004,511Memory device having separate programming and resistance readout control202110,991,881Method for controlling the forming voltage in resistive random access memory devices202110,991,763Vertical array of resistive switching devices having restricted filament regions and tunable top electrode volume202110,985,069Gate stack optimization for wide and narrow nanosheet transistor devices202110,978,551Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor202110,971,593Oxygen reservoir for low threshold voltage P-type MOSFET202110,971,407Method of forming a complementary metal oxide semiconductor device having fin field effect transistors with a common metal gate202110,971,549Semiconductor memory device having a vertical active region202110,964,603Hybrid gate stack integration for stacked vertical transport field-effect transistors202110,957,937Three-terminal copper-driven neuromorphic device202110,957,742Resistive random-access memory array with reduced switching resistance variability202110,950,662Resistive memory device with meshed electrodes202110,950,787Method having resistive memory crossbar array employing selective barrier layer growth202110,943,787Confined work function material for gate-all around transistor devices202110,943,924Semiconductor-on-insulator finFET devices with high thermal conductivity dielectrics202110,943,903Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy202110,937,883Vertical transport FETs having a gradient threshold voltage202110,930,762Multiple work function nanosheet field effect transistor using sacrificial silicon germanium growth202110,923,403Co-integration of high carrier mobility PFET and NFET devices on the same substrate using low temperature condensation202110,915,811Intercalation cells for multi-task learning202110,916,432Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device202110,916,699Resistive memory crossbar array employing selective barrier layer growth202110,916,659Asymmetric threshold voltage FinFET device by partial channel doping variation202110,907,702Transmission device202110,903,424Resistive RAM cell structure for gradual set programming202110,903,425Oxygen vacancy and filament-loss protection for resistive switching devices202110,903,421Controlling filament formation and location in a resistive random-access memory device202110,896,965Formation of wrap-around-contact to reduce contact resistivity202110,896,962Asymmetric threshold voltages in semiconductor devices202110,892,408Multivalent oxide cap for analog switching resistive memory202110,885,979Paired intercalation cells for drift migration202110,886,362Multilayer dielectric for metal-insulator-metal capacitor (MIMCAP) capacitance and leakage improvement202110,886,369Formation of self-limited inner spacer for gate-all-around nanosheet FET202110,886,467CBRAM by subtractive etching of metals202110,886,376Formation of wrap-around-contact to reduce contact resistivity202110,886,334Vertical array of resistive switching devices having a tunable oxygen vacancy concentration20219,078,294'Nanoheater elements, systems and methods of use thereof'20156,936,118'Process of forming a composite coating on a substrate'20055,225,004'Bulk rapidly solifidied magnetic materials'19934,991,501'Dampening water feed roller for planographic printing press'19914,082,718'Tap hole mix'1978Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1978–1991Patents assigned to NIPPON STEEL CORP (2)· patent assignee history
1991Patents assigned to AKYAMA INSATSUKI SEIZO KK (1)· patent assignee history
1993Based in Watertown, MA, US· patent location history
2005–2015Based in Belmont, MA, US· patent location history
2015Patents assigned to ANDO TEIICHI (1)· patent assignee history
2021Patents assigned to IBM (35)· patent assignee history
2021Patents assigned to AISIN AW CO (1)· patent assignee history
2021Based in Tuckahoe, NY, US· patent location history
2021Based in Eastchester, NY, US· patent location history
2021Based in Okazaki, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 35 | 2021 |
| NIPPON STEEL CORP | 2 | 1978–1991 |
| AISIN AW CO | 1 | 2021 |
| AKYAMA INSATSUKI SEIZO KK | 1 | 1991 |
| ANDO TEIICHIself | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tuckahoe, New York, US | 31 | 2021 |
| Eastchester, New York, US | 5 | 2021 |
| Belmont, Massachusetts, US | 2 | 2005–2015 |
| Okazaki, JP | 1 | 2021 |
| Watertown, Massachusetts, US | 1 | 1993 |