Inventor
Donald M. Archer
Inventor
Santa Clara, CA, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H03FAmplifiers15%
G05FSystems for regulating electric or magnetic variables8%
G11CStatic stores8%
H03KPulse technique8%
PatentTitleYear
8,735,980'Configuration and fabrication of semiconductor structure using empty and filled wells'20148,629,027'Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions'20148,377,768'Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses'20138,304,835'Configuration and fabrication of semiconductor structure using empty and filled wells'20128,101,479'Fabrication of asymmetric field-effect transistors using L-shaped spacers'20128,084,827'Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses'20117,968,921'Asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions'20117,480,190'Known default data state EPROM'20096,775,112'Apparatus and method for improving ESD and transient immunity in shunt regulators'20046,605,979'Trim bit circuit for band-gap reference'20035,844,299'Integrated inductor'19985,808,513'Rail-to-rail input common mode range differential amplifier that operates with very low rail-to-rail voltages'19985,764,101'Rail-to-rail input common mode range differential amplifier that operates with very low rail-to-rail voltages'19985,386,160'Trim correction circuit with temperature coefficient compensation'19955,311,115'Enhancement-depletion mode cascode current mirror'19945,200,654'Trim correction circuit with temperature coefficient compensation'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2014Patents assigned to NAT SEMICONDUCTOR CORP (15)· patent assignee history
1993–1995Based in Sunnyvale, CA, US· patent location history
1998–2014Based in Santa Clara, CA, US· patent location history
2011–2014Patents assigned to ARCHER DONALD M (5)· patent assignee history
2011–2014Patents assigned to BAHL SANDEEP R (5)· patent assignee history
2011–2014Patents assigned to BULUCEA CONSTANTIN (5)· patent assignee history
2011–2014Patents assigned to FRENCH WILLIAM D (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 15 | 1993–2014 |
| ARCHER DONALD Mself | 5 | 2011–2014 |
| BAHL SANDEEP R | 5 | 2011–2014 |
| BULUCEA CONSTANTIN | 5 | 2011–2014 |
| FRENCH WILLIAM D | 5 | 2011–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 13 | 1998–2014 |
| Sunnyvale, California, US | 3 | 1993–1995 |