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Inventor

Fu-Chieh Hsu

Inventor
Saratoga, CA, US

Overview

65→
Patents
1988–2012
Patent span
Electricity
Primary field (CPC H)

Patents· 65 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores22%
H10DInorganic electric semiconductor devices18%
G06FElectric digital data processing15%
H10BElectronic memory devices14%
H04LTransmission of digital information, e.g. telegraphic communication8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
G09GArrangements or circuits for control of indicating devices using static means to present variable information1%
PatentTitleYear
8,286,119'Systematic method for variable layout shrink'20128,030,181'Electrical fuse circuit for security applications'20117,821,041'Electrical fuse circuit for security applications'20107,634,707'Error detection/correction method'20097,505,345'Circuit and method for an SRAM with two phase word line pulse'20097,353,438'Transparent error correcting memory'20087,323,379'Fabrication process for increased capacitance in an embedded DRAM memory'20087,206,913'High speed memory system'20077,056,785'Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same'20067,051,264'Error correcting memory and method of operating same'20066,964,895'Method of fabricating vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region'20056,913,964'Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region'20056,841,821'Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same'20056,808,169'Non-volatile memory with crown electrode to increase capacitance between control gate and floating gate'20046,784,048'Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage'20046,754,746'Memory array with read/write methods'20046,744,676'DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same'20046,717,864'Latched sense amplifiers as high speed memory in a memory system'20046,686,624'Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region'20046,661,042'One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region'20036,654,295'Reduced topography DRAM cell fabricated using a modified logic process and method for operating same'20036,642,098'DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same'20036,573,548'DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same'20036,512,691'Non-volatile memory embedded in a conventional logic process'20036,509,595'DRAM cell fabricated using a modified logic process and method for operating same'20036,510,492'Apparatus for controlling data transfer between a bus and memory array and method for operating same'20036,483,755'Memory modules with high speed latched sense amplifiers'20026,468,855'Reduced topography DRAM cell fabricated using a modified logic process and method for operating same'20026,457,108'Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory'20026,442,060'High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process'20026,425,046'Method for using a latched sense amplifier in a memory module as a high-speed cache memory'20026,393,504'Dynamic address mapping and redundancy in a modular memory device'20026,370,052'Method and structure of ternary CAM cell in logic process'20026,329,240'Non-volatile memory cell and methods of fabricating and operating same'20016,295,593'Method of operating memory array with write buffers and related apparatus'20016,272,577'Data processing system with master and slave devices and asymmetric signal swing bus'20016,147,914'On-chip word line voltage generation for DRAM embedded in logic process'20006,128,700'System utilizing a DRAM array as a next level cache memory and method for operating same'20006,075,720'Memory cell for DRAM embedded in logic'20005,999,474'Method and apparatus for complete hiding of the refresh of a semiconductor memory'19995,940,088'Method and structure for data traffic reduction for display refresh'19995,923,593'Multi-port DRAM cell and memory system using same'19995,843,799'Circuit module redundancy architecture process'19985,831,467'Termination circuit with power-down mode for use in circuit module architecture'19985,829,026'Method and structure for implementing a cache memory using a DRAM array'19985,790,138'Method and structure for improving display data bandwidth in a unified memory architecture system'19985,737,587'Resynchronization circuit for circuit module architecture'19985,729,152'Termination circuits for reduced swing signal lines and methods for operating same'19985,666,480'Fault-tolerant hierarchical bus system and method of operating same'19975,655,113'Resynchronization circuit for a memory system and method of operating same'19975,613,077'Method and circuit for communication between a module and a bus controller in a wafer-scale integrated circuit system'19975,592,632'Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system'19975,576,554'Wafer-scale integrated circuit interconnect structure architecture'19965,511,020'Pseudo-nonvolatile memory incorporating data refresh operation'19965,498,990'Reduced CMOS-swing clamping circuit for bus lines'19965,498,886'Circuit module redundancy architecture'19965,265,047'High density SRAM circuit with single-ended memory cells'19935,166,556'Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits'19925,128,731'Static random access memory cell using a P/N-MOS transistors'19925,019,771'Contact sensing for integrated circuit testing'19914,997,783'Static ram cell with trench pull-down transistors and buried-layer ground plate'19914,987,090'Static ram cell with trench pull-down transistors and buried-layer ground plate'19914,876,215'Method of making a static ram cell with trench pull-down transistors and buried-layer ground plate'19894,843,023'Process for forming lightly-doped-drain (LDD) without extra masking steps'19894,794,561'Static ram cell with trench pull-down transistors and buried-layer ground plate'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–1992Patents assigned to INTEGRATED DEVICE TECH (5)· patent assignee history
1988–1989Based in Cupertino, CA, US· patent location history
1991–1992Patents assigned to KNIGHTS TECHNOLOGY INC (2)· patent assignee history
1991–2009Based in Saratoga, CA, US· patent location history
1996–2007Patents assigned to MONOLITHIC SYSTEM TECH INC (47)· patent assignee history
1996Based in Saratogo, CA, US· patent location history
2008–2009Patents assigned to MOSYS INC (3)· patent assignee history
2009–2012Patents assigned to TAIWAN SEMICONDUCTOR MFG (4)· patent assignee history
2009–2012Based in Hsinchu, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MONOLITHIC SYSTEM TECH INC471996–2007
INTEGRATED DEVICE TECH51988–1992
TAIWAN SEMICONDUCTOR MFG42009–2012
MOSYS INC32008–2009
KNIGHTS TECHNOLOGY INC21991–1992
Locations
LocationPatentsSpan
Saratoga, California, US571991–2009
Hsinchu, TW42009–2012
Cupertino, California, US31988–1989
Saratogo, California, US11996