Inventor

Takahiro Onai

Inventor

Ome, JP

Overview

1990–2013

Patent span

Electricity

Primary field (CPC H)

Patents· 21 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices51%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

C30BSingle-crystal growth3%

G11CStatic stores3%

H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light3%

H03KPulse technique3%

H10HInorganic light-emitting semiconductor devices having potential barriers3%

PatentTitleYear

8,436,333'Silicon light emitting diode, silicon optical transistor, silicon laser and its manufacturing method'2013 7,405,588'Device and data processing method employing the device'2008 7,042,055'Semiconductor device and manufacturing thereof'2006 7,042,051'Semiconductor device including impurity layer having a plurality of impurity peaks formed beneath the channel region'2006 7,029,988'Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium'2006 6,982,465'Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics'2006 6,878,606'Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium'2005 6,667,199'Semiconductor device having a replacement gate type field effect transistor and its manufacturing method'2003 6,524,903'Method of manufacturing a semiconductor device having two peaks in an impurity concentration distribution'2003 6,313,012'Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator'2001 6,004,865'Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator'1999 5,962,880'Heterojunction bipolar transistor'1999 5,598,015'Hetero-junction bipolar transistor and semiconductor devices using the same'1997 5,523,602'Multi-layered structure having single crystalline semiconductor film formed on insulator'1996 5,430,317'Semiconductor device'1995 5,424,575'Semiconductor device for SOI structure having lead conductor suitable for fine patterning'1995 5,387,545'Impurity diffusion method'1995 5,324,983'Semiconductor device'1994 5,177,584'Semiconductor integrated circuit device having bipolar memory, and method of manufacturing the same'1993 5,109,263'Semiconductor device with optimal distance between emitter and trench isolation'1992 4,926,235'Semiconductor device'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2013Patents assigned to ONAI TAKAHIRO (2)· patent assignee history

1990Patents assigned to HAYASHIDA TETSUYA (1)· patent assignee history

1990–1992Based in Hachioji, JP· patent location history

1992–2013Patents assigned to HITACHI LTD (15)· patent assignee history

1993Based in Tokyo, JP· patent location history

1994–2006Based in Ome, JP· patent location history

2005–2006Patents assigned to RENESAS TECH CORP (5)· patent assignee history

2006Based in Kokubunji, JP· patent location history

2008–2013Based in Kodaira, JP· patent location history

2013Patents assigned to ARAI TADASHI (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
HITACHI LTD	15	1992–2013
RENESAS TECH CORP	5	2005–2006
ONAI TAKAHIROself	2	1990–2013
ARAI TADASHI	1	2013
HAYASHIDA TETSUYA	1	1990

Locations

Location	Patents	Span
Ome, JP	15	1994–2006
Kodaira, JP	2	2008–2013
Hachioji, JP	2	1990–1992
Kokubunji, JP	1	2006
Tokyo, JP	1	1993