Inventor
Nicholas J. Kepler
Inventor
Saratoga, CA, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H10DInorganic electric semiconductor devices23%
G11CStatic stores7%
G01RMeasuring electric variables3%
H10BElectronic memory devices3%
PatentTitleYear
7,737,021'Resist trim process to define small openings in dielectric layers'20107,026,691'Minimizing transistor size in integrated circuits'20066,600,333'Method and test structure for characterizing sidewall damage in a semiconductor device'20036,500,755'Resist trim process to define small openings in dielectric layers'20026,406,993'Method of defining small openings in dielectric layers'20026,383,906'Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption'20026,313,538'Semiconductor device with partial passivation layer'20016,287,953'Minimizing transistor size in integrated circuits'20016,268,255'Method of forming a semiconductor device with metal silicide regions'20016,191,034'Forming minimal size spaces in integrated circuit conductive lines'20016,146,954'Minimizing transistor size in integrated circuits'20006,051,881'Forming local interconnects in integrated circuits'20006,046,088'Method for self-aligning polysilicon gates with field isolation and the resultant structure'20005,930,659'Forming minimal size spaces in integrated circuit conductive lines'19995,844,836'Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell'19985,796,651'Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2006Patents assigned to ADVANCED MICRO DEVICES INC (14)· patent assignee history
1998–2010Based in Saratoga, CA, US· patent location history
1998–2006Based in San Jose, CA, US· patent location history
1999Patents assigned to ADVANCED MICRODEVICES INC (1)· patent assignee history
2010Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 14 | 1998–2006 |
| ADVANCED MICRODEVICES INC | 1 | 1999 |
| GLOBALFOUNDRIES INC | 1 | 2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 8 | 1998–2010 |
| San Jose, California, US | 8 | 1998–2006 |