Inventor
Andreas Jakobs
Inventor
München, DE
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores54%
G06FElectric digital data processing11%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses11%
H03KPulse technique7%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
H04LTransmission of digital information, e.g. telegraphic communication4%
H05KPrinted circuits4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
PatentTitleYear
7,888,948'Controlling an analog signal in an integrated circuit'20117,737,742'Delay locked loop'20107,646,650'Buffer component for a memory module, and a memory module and a memory system having such buffer component'20107,573,741'Method and circuit arrangements for adjusting signal propagation times in a memory system'20097,518,935'Synchronous RAM memory circuit'20097,457,174'Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted'20087,456,665'Phase shifter'20087,386,696'Semiconductor memory module'20087,339,407'DLL circuit for providing an adjustable phase relationship with respect to a periodic input signal'20087,315,969'Memory module with a test device'20087,224,636'Semiconductor memory module'20077,149,864'Method and circuit for allocating memory arrangement addresses'20067,120,077'Memory module having a plurality of integrated memory components'20067,061,784'Semiconductor memory module'20067,016,259'Apparatus for calibrating the relative phase of two reception signals of a memory chip'20067,013,374'Integrated memory and method for setting the latency in the integrated memory'20066,982,893'Memory module having a plurality of integrated memory components'20066,972,981'Semiconductor memory module'20056,909,657'Pseudostatic memory circuit'20056,791,358'Circuit configuration with signal lines for serially transmitting a plurality of bit groups'20046,457,168'Method for producing structures on the surface of a semiconductor wafer'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2010Patents assigned to INFINEON TECHNOLOGIES AG (18)· patent assignee history
2002–2004Based in Mnchen, DE· patent location history
2005–2010Based in München, DE· patent location history
2008–2011Patents assigned to QIMONDA AG (3)· patent assignee history
2008–2011Based in Munich, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 18 | 2002–2010 |
| QIMONDA AG | 3 | 2008–2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| München, DE | 14 | 2005–2010 |
| Munich, DE | 5 | 2008–2011 |
| Mnchen, DE | 2 | 2002–2004 |