Inventor

Sunil D. Mehta

Inventor

San Jose, CA, US

Overview

1996–2019

Patent span

Electricity

Primary field (CPC H)

Patents· 103 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%

H10BElectronic memory devices19%

H10DInorganic electric semiconductor devices17%

G11CStatic stores13%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%

C07KPeptides3%

A61KPreparations for medical, dental or toiletry purposes2%

C12MApparatus for enzymology or microbiology2%

C12NMicroorganisms or enzymes2%

PatentTitleYear

10,208,283Methods and systems for manipulating particles using a fluidized bed2019 9,839,920'Apparatus for manipulating particles using at least one chamber having an inlet and an opposed outlet'2017 9,292,648'Activity-driven capacitance reduction to reduce dynamic power consumption in an integrated circuit'2016 9,279,133'Methods and systems for manipulating particles using a fluidized bed'2016 9,255,022'Biological-chemical treatment of liquid organic wastewater'2016 9,090,910'Methods and systems for manipulating particles using a fluidized bed'2015 7,989,911'Shallow trench isolation (STI) with trench liner of increased thickness'2011 7,985,656'Shallow trench isolation (STI) with trench liner of increased thickness'2011 7,897,448'Formation of high voltage transistor with high breakdown voltage'2011 7,420,037'Heat shock protein-based vaccines and immunotherapies'2008 RE040311'Zero-power programmable memory cell'2008 7,309,491'Heat shock protein-based vaccines and immunotherapies'2007 7,301,182'Circuit layout for improved performance while preserving or improving density'2007 7,242,053'EEPROM device with voltage-limiting charge pump circuit'2007 7,078,286'Process for fabricating a semiconductor device having electrically isolated low voltage and high voltage regions'2006 6,977,408'High-performance non-volatile memory device and fabrication process'2005 6,846,714'Voltage limited EEPROM device and process for fabricating the device'2005 6,841,447'EEPROM device having an isolation-bounded tunnel capacitor and fabrication process'2005 6,833,602'Device having electrically isolated low voltage and high voltage regions and process for fabricating the device'2004 6,737,702'Zero power memory cell with reduced threshold voltage'2004 6,716,705'EEPROM device having a retrograde program junction region and process for fabricating the device'2004 6,660,579'Zero power memory cell with improved data retention'2003 6,649,514'EEPROM device having improved data retention and process for fabricating the device'2003 6,611,463'Zero-power programmable memory cell'2003 6,600,188'EEPROM with a neutralized doping at tunnel window edge'2003 6,596,587'Shallow junction EEPROM device and process for fabricating the device'2003 6,577,007'Manufacturing process for borderless vias with respect to underlying metal'2003 6,570,212'Complementary avalanche injection EEPROM cell'2003 6,545,313'EEPROM tunnel window for program injection via P contacted inversion'2003 6,524,911'Combination of BPTEOS oxide film with CMP and RTA to achieve good data retention'2003 6,515,899'Non-volatile memory cell with enhanced cell drive current'2003 6,489,806'Zero-power logic cell for use in programmable logic devices'2002 6,472,308'Borderless vias on bottom metal'2002 6,455,912'Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress'2002 6,455,593'Method of dynamic retardation of cell cycle kinetics to potentiate cell damage'2002 6,455,375'Eeprom tunnel window for program injection via P contacted inversion'2002 6,424,000'Floating gate memory apparatus and method for selected programming thereof'2002 6,424,003'EEPROM cell with self-aligned tunneling window'2002 6,362,527'Borderless vias on bottom metal'2002 6,326,663'Avalanche injection EEPROM memory cell with P-type control gate'2001 6,309,942'STI punch-through defects and stress reduction by high temperature oxide reflow process'2001 6,303,949'Method and system for providing electrical insulation for local interconnect in a logic circuit'2001 6,297,128'Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress'2001 6,291,327'Optimization of S/D annealing to minimize S/D shorts in memory array'2001 6,287,916'Method for forming a semiconductor device using LPCVD nitride to protect floating gate from charge loss'2001 6,282,123'Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell'2001 6,274,898'Triple-well EEPROM cell using P-well for tunneling across a channel'2001 6,274,576'Method of dynamic retardation of cell cycle kinetics to potentiate cell damage'2001 6,261,944'Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect'2001 6,255,169'Process for fabricating a high-endurance non-volatile memory device'2001 6,232,221'Borderless vias'2001 6,232,223'High integrity borderless vias with protective sidewall spacer'2001 6,232,631'Floating gate memory cell structure with programming mechanism outside the read path'2001 6,221,733'Reduction of mechanical stress in shallow trench isolation process'2001 6,215,700'PMOS avalanche programmed floating gate memory cell structure'2001 6,214,666'Method of forming a non-volatile memory device'2001 6,211,022'Field leakage by using a thin layer of nitride deposited by chemical vapor deposition'2001 6,208,559'Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb'2001 6,207,989'Non-volatile memory device having a high-reliability composite insulation layer'2001 6,197,638'Oxide formation process for manufacturing programmable logic device'2001 6,190,966'Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration'2001 6,184,105'Method for post transistor isolation'2001 6,172,392'Boron doped silicon capacitor plate'2001 6,166,428'Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon'2000 6,097,090'High integrity vias'2000 6,093,946'EEPROM cell with field-edgeless tunnel window using shallow trench isolation process'2000 6,087,696'Stacked tunneling dielectric technology for improving data retention of EEPROM cell'2000 6,087,275'Reduction of n-channel parasitic transistor leakage by using low power/low pressure phosphosilicate glass'2000 6,075,724'Method for sorting semiconductor devices having a plurality of non-volatile memory cells'2000 6,075,293'Semiconductor device having a multi-layer metal interconnect structure'2000 6,071,784'Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss'2000 6,064,595'Floating gate memory apparatus and method for selected programming thereof'2000 6,064,105'Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide'2000 6,060,766'Protection of hydrogen sensitive regions in semiconductor devices from the positive charge associated with plasma deposited barriers or layers'2000 6,040,019'Method of selectively annealing damaged doped regions'2000 6,034,893'Non-volatile memory cell having dual avalanche injection elements'2000 6,028,789'Zero-power CMOS non-volatile memory cell having an avalanche injection element'2000 6,025,637'Spacer-based antifuse structure for low capacitance and high reliability and method of fabrication thereof'2000 6,009,033'Method of programming and erasing an EEPROM device under an elevated temperature and apparatus thereof'1999 5,999,449'Two transistor EEPROM cell using P-well for tunneling across a channel'1999 5,989,957'Process for fabricating semiconductor memory device with high data retention including silicon oxynitride etch stop layer formed at high temperature with low hydrogen ion concentration'1999 5,982,035'High integrity borderless vias with protective sidewall spacer'1999 5,969,992'EEPROM cell using P-well for tunneling across a channel'1999 5,960,274'Oxide formation process for manufacturing programmable logic device'1999 5,956,610'Method and system for providing electrical insulation for local interconnect in a logic circuit'1999 5,942,780'Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate'1999 5,940,735'Reduction of charge loss in nonvolatile memory cells by phosphorus implantation into PECVD nitride/oxynitride films'1999 5,925,932'Borderless vias'1999 5,908,308'Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve isolation in a transistor array'1999 5,904,575'Method and apparatus incorporating nitrogen selectively for differential oxide growth'1999 5,885,904'Method to incorporate, and a device having, oxide enhancement dopants using gas immersion laser doping (GILD) for selectively growing an oxide layer'1999 5,854,114'Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide'1998 5,841,701'Method of charging and discharging floating gage transistors to reduce leakage current'1998 5,830,795'Simplified masking process for programmable logic device manufacture'1998 5,795,627'Method for annealing damaged semiconductor regions allowing for enhanced oxide growth'1998 5,789,269'Field implant for semiconductor device'1998 5,756,367'Method of making a spacer based antifuse structure for low capacitance and high reliability'1998 5,679,599'Isolation using self-aligned trench formation and conventional LOCOS'1997 5,672,521'Method of forming multiple gate oxide thicknesses on a wafer substrate'1997 5,646,063'Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device'1997 5,619,072'High density multi-level metallization and interconnection structure'1997 5,604,370'Field implant for semiconductor device'1997 5,587,945'CMOS EEPROM cell with tunneling window in the read path'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2003Patents assigned to ADVANCED MICRO DEVICES INC (41)· patent assignee history

1996–2011Based in San Jose, CA, US· patent location history

1999–2002Patents assigned to VANTIS CORP (22)· patent assignee history

2000–2011Patents assigned to LATTICE SEMICONDUCTOR CORP (31)· patent assignee history

2001–2002Based in Rumford, RI, US· patent location history

2015–2017Patents assigned to HERMAN TOD (3)· patent assignee history

2015–2017Patents assigned to MCMAHON JOE (3)· patent assignee history

2015–2019Based in Morrisville, NC, US· patent location history

2016Based in Pleasanton, CA, US· patent location history

2016Based in Henrico, VA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	41	1996–2003
LATTICE SEMICONDUCTOR CORP	31	2000–2011
VANTIS CORP	22	1999–2002
HERMAN TOD	3	2015–2017
MCMAHON JOE	3	2015–2017

Locations

Location	Patents	Span
San Jose, California, US	92	1996–2011
Morrisville, NC, US	4	2015–2019
Rumford, RI, US	2	2001–2002
Pleasanton, California, US	1	2016
Henrico, Virginia, US	1	2016